公开(公告)号：US20050138341A1

公开(公告)日：2005-06-23

申请号：US10739689

申请日：2003-12-17

申请人： Subramaniam Maiyuran ,  Peter Smith ,  Stephan Jourdan

发明人： Subramaniam Maiyuran ,  Peter Smith ,  Stephan Jourdan

IPC分类号： G06F9/00 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/325 ,  G06F9/3808 ,  G06F9/3844

摘要： A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.

摘要翻译： 公开了一种用于预测环路结束的环路预测器的方法和装置。 在一个实施例中，环路预测器可以具有预测计数器，以保持预测计数，该预测计数表示在给定循环的执行期间预测器炖值将重复的预期次数。 循环预测器还可以具有一个或多个运行计数器，以在执行当前循环期间保持炖煮值重复的次数的计数。 当计数器值匹配时，预测器可以发出循环结束的预测。

公开(公告)号：US07457917B2

公开(公告)日：2008-11-25

申请号：US11027413

申请日：2004-12-29

申请人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

发明人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F1/00

CPC分类号： G06F12/0875 ,  G06F9/3802 ,  G06F9/3804 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括高速缓冲存储器，其可以是具有多个存储体的顺序高速缓存。 每个存储体包括数据阵列，耦合到数据阵列的解码器以选择一组数据阵列，以及读出放大器。 只有要访问的存储体可以被供电，并且在一些实施例中，可以使用早期路径信息来维持处于功率降低状态的剩余存储体。 在一些实施例中，可以使用时钟选通来维持处于功率降低状态的高速缓冲存储器的各种组件。 描述和要求保护其他实施例。

公开(公告)号：US20060218351A1

公开(公告)日：2006-09-28

申请号：US11414541

申请日：2006-05-01

申请人： Peter Smith ,  Satish Damaraju ,  Subramaniam Maiyuran

发明人： Peter Smith ,  Satish Damaraju ,  Subramaniam Maiyuran

IPC分类号： G06F12/00

CPC分类号： G06F9/3808 ,  G06F12/123 ,  G06F12/127

摘要： A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim set from a sequentially accessed memory; selecting a victim way for the selected victim set; reading a next way pointer from a trace line of a trace currently stored in the selected victim way, if the selected victim way has the next way pointer; and writing a next line of the new trace into the selected victim way over the trace line of the currently stored trace. The method also includes forcing a replacement algorithm of next set to select a victim way of the next set using the next way pointer, if the trace line of the currently stored trace is not an active trace tail line.

公开(公告)号：US20060036834A1

公开(公告)日：2006-02-16

申请号：US10917582

申请日：2004-08-13

申请人： Subramaniam Maiyuran ,  Peter Smith ,  Varghese George ,  Eran Altshuler ,  Robert Valentine ,  Zeev Offen ,  Oded Lempel

发明人： Subramaniam Maiyuran ,  Peter Smith ,  Varghese George ,  Eran Altshuler ,  Robert Valentine ,  Zeev Offen ,  Oded Lempel

IPC分类号： G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/325

摘要： A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.

摘要翻译： 一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。 更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距 高速缓存访​​问并增加可以在处理器内执行uop的速率。

公开(公告)号：US07689772B2

公开(公告)日：2010-03-30

申请号：US11418883

申请日：2006-05-04

申请人： Satish Damaraju ,  Subramaniam Maiyuran ,  Truyen Trinh ,  Parag Raval ,  Peter Smith

发明人： Satish Damaraju ,  Subramaniam Maiyuran ,  Truyen Trinh ,  Parag Raval ,  Peter Smith

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0864 ,  G06F12/123 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

摘要： The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.

摘要翻译： N路集合关联顺序高速缓存中的方式的数量被调制以交易功率和性能。 在基于地址的分配期间，路由选择被限制，使得只有N个路径的子集被用于允许不使用的N路被关闭的一系列地址。

公开(公告)号：US20070260818A1

公开(公告)日：2007-11-08

申请号：US11418883

申请日：2006-05-04

申请人： Satish Damaraju ,  Subramaniam Maiyuran ,  Truyen Trinh ,  Parag Raval ,  Peter Smith

发明人： Satish Damaraju ,  Subramaniam Maiyuran ,  Truyen Trinh ,  Parag Raval ,  Peter Smith

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/123 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

摘要： The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.

摘要翻译： N路集合关联顺序高速缓存中的方式的数量被调制以交易功率和性能。 在基于地址的分配期间，路由选择被限制，使得只有N个路径的子集被用于允许不使用的N路被关闭的一系列地址。

公开(公告)号：US20060143382A1

公开(公告)日：2006-06-29

申请号：US11027413

申请日：2004-12-29

申请人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

发明人： Satish Damaraju ,  Subramaniam Maiyuran ,  Peter Smith ,  Navin Monteiro

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3802 ,  G06F9/3804 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括高速缓冲存储器，其可以是具有多个存储体的顺序高速缓存。 每个存储体包括数据阵列，耦合到数据阵列的解码器以选择一组数据阵列，以及读出放大器。 只有要访问的存储体可以被供电，并且在一些实施例中，可以使用早期路径信息来维持处于功率降低状态的剩余存储体。 在一些实施例中，可以使用时钟选通来维持处于功率降低状态的高速缓冲存储器的各种组件。 描述和要求保护其他实施例。

公开(公告)号：US20050044318A1

公开(公告)日：2005-02-24

申请号：US10646033

申请日：2003-08-22

申请人： Subramaniam Maiyuran ,  Peter Smith ,  Niranjan Cooray ,  Asim Nisar

发明人： Subramaniam Maiyuran ,  Peter Smith ,  Niranjan Cooray ,  Asim Nisar

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3802 ,  G06F9/3808

摘要： A method and apparatus for a trace end predictor for a trace cache is disclosed. In one embodiment, the trace end predictor may have one or more buffers to contain a head address for a subsequent trace. The head address may include the way number and set number of the next head, along with partial stew data to support additional execution predictors. The buffers may also include tag data of the current trace's tail address, and may additionally include control bits for determining whether to replace the buffer's contents with information from another trace's tail. Reading the next head address from the trace end predictor, as opposed to reading it from the trace cache array, may reduce certain execution time delays.

摘要翻译： 公开了一种用于跟踪高速缓存的跟踪结束预测器的方法和装置。 在一个实施例中，跟踪结束预测器可以具有一个或多个缓冲器以包含后续跟踪的头地址。 头部地址可以包括下一个头部的路径编号和编号，以及部分炖菜数据以支持附加的执行预测器。 缓冲器还可以包括当前迹线的尾部地址的标签数据，并且还可以包括用于确定是否用来自另一跟踪尾部的信息替换缓冲器内容的控制位。 从跟踪结束预测器读取下一个头地址，而不是从跟踪高速缓存阵列读取它，可能会减少某些执行时间延迟。

公开(公告)号：US20160210968A1

公开(公告)日：2016-07-21

申请号：US14598958

申请日：2015-01-16

申请人： Lisa Ouakil ,  Abdelhamid Ouakil ,  Ouns Mouri ,  Peter Smith

发明人： Lisa Ouakil ,  Abdelhamid Ouakil ,  Ouns Mouri ,  Peter Smith

IPC分类号： G10L15/28 ,  G06F17/27 ,  G10L15/065

CPC分类号： G06F17/274 ,  G06F17/2765 ,  G06F17/2785 ,  G10L15/183 ,  G10L2015/228

摘要： The invention is system and method to recognize speech vocalizations using context-specific grammars and vocabularies. The system and method allow increased accuracy of recognized utterances by eliminating all language encodings irrelevant to the current context and allowing identification of appropriate context transitions. The system and method creates a context dependent speech recognition system with multiple supported contexts, each with specific grammar and vocabulary, and each identifying the potential context transition allowed. The system and method also include programmatic integration between the context dependent speech recognition system and other systems to make use of the recognized speech.

摘要翻译： 本发明是使用上下文特定语法和词汇识别语音发声的系统和方法。 该系统和方法允许通过消除与当前上下文无关的所有语言编码并允许识别适当的上下文转换来增加识别话语的准确性。 系统和方法创建具有多个支持的上下文的上下文相关语音识别系统，每个具有特定语法和词汇，并且每个识别允许的潜在上下文转换。 系统和方法还包括上下文相关语音识别系统与其他系统之间的程序化集成，以利用所识别的语音。

公开(公告)号：US09164768B2

公开(公告)日：2015-10-20

申请号：US13333939

申请日：2011-12-21

申请人： Peter Smith ,  David Richard Hargreaves

发明人： Peter Smith ,  David Richard Hargreaves

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/30185 ,  G06F9/3016

摘要： A method of executing an instruction set having a first instruction and a second instruction, includes: reading the first instruction; determining whether the first instruction is integral with the second instruction; reading the second instruction; when the first instruction is integral with the second instruction, interpreting a first operator field of the second instruction to represent a first operator; and when the first instruction is not integral with the second instruction, interpreting the first operator field of the second instruction to represent a second operator, wherein the first operator is different to the second operator.

摘要翻译： 一种执行具有第一指令和第二指令的指令集的方法，包括：读取第一指令; 确定所述第一指令是否与所述第二指令成一体; 阅读第二条指令 当第一指令与第二指令成一体时，解释第二指令的第一操作符字段来表示第一操作符; 并且当第一指令不与第二指令成一体时，解释第二指令的第一操作符字段来表示第二操作符，其中第一操作符与第二操作符不同。