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公开(公告)号：US06631093B2
公开(公告)日：2003-10-07
申请号：US09895361
申请日：2001-06-29
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.
摘要翻译： 低功耗存储器位线预充电方案。 存储器位线耦合到第一读取预充电器件。 第二写入预充电装置也耦合到存储器位线，并且仅在响应于存储器写入操作时被使能。 第一读取和第二写入预充电装置的尺寸使其组合的驱动强度足以在写操作之后的预充电期间对第一存储器位线进行预充电。
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公开(公告)号：US06629194B2
公开(公告)日：2003-09-30
申请号：US09872965
申请日：2001-05-31
IPC分类号： G06F1200
CPC分类号： G06F9/30141 , G06F9/3012 , G11C7/12 , G11C2207/007 , G11C2207/2281
摘要： A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.
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公开(公告)号：US06628539B2
公开(公告)日：2003-09-30
申请号：US09872975
申请日：2001-05-31
IPC分类号： G11C1900
CPC分类号： G11C11/419 , G06F9/30036 , G06F9/30105 , G06F9/3012 , G06F9/30141
摘要： A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.
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4.发明授权Single stage pulsed domino circuit for driving cascaded skewed static logic circuits 有权用于驱动级联偏移静态逻辑电路的单级脉冲多米诺电路公开(公告)号：US06833735B2
公开(公告)日：2004-12-21
申请号：US10335141
申请日：2002-12-31
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.
摘要翻译： 一种互补的金属氧化物半导体（CMOS）低功耗高速逻辑电路，由级联的级联链组成。 第一级是具有用于接收数据信号的一个或多个逻辑信号输入的脉冲多米诺逻辑电路，以及用于接收时钟脉冲的定时输入，用于在简短的时间窗口期间控制输入脉冲多米诺骨架级以进行评估。 脉冲多米诺骨电路的输出连接到串联连接的偏斜静态逻辑门，每条链的上拉和下拉晶体管的沟道尺寸与产品的栅极到栅极的静态 逻辑链，用于传送所述输入数据信号前沿的信息的交替快速高到低和从低到高的转变。 使用脉冲多米诺骨牌第一阶段驱动偏斜逻辑静态门链降低了功耗，但保留了常规多米诺逻辑电路的速度。
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公开(公告)号：US06341099B1
公开(公告)日：2002-01-22
申请号：US09672950
申请日：2000-09-29
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.
摘要翻译： 一种用于降低由多个数据单元组成的数据存储设备中的功耗的技术包括将数据单元的数量排列成簇，每个簇具有多个数据单元，其数据使能输入连接在一起。 提供数据写总线以向数据单元数量的数据使能输入提供数据使能信号。 在簇和写入数据总线之间分别设置多个通过门。 通过门有选择地使允许数据使能信号从写入数据总线传递到所选择的一个或多个集群的多个数据单元的数据使能输入。 多个反相器可以分别设置在通过门数和簇之间。 多个保持器电路可以分别连接到通孔的数量。 每个通过栅极可以包括一对场效应晶体管，其可以是互补场效应晶体管。 每个维持器电路可以包括一对背对背反相器。
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公开(公告)号：US06292029B1
公开(公告)日：2001-09-18
申请号：US09471650
申请日：1999-12-23
申请人： Sudarshan Kumar , Wenjie Jiang
发明人： Sudarshan Kumar , Wenjie Jiang
IPC分类号： H03K19096
CPC分类号： H03K19/00338 , H03K19/096
摘要： A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
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公开(公告)号：US6111435A
公开(公告)日：2000-08-29
申请号：US343961
申请日：1999-06-30
申请人： Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
发明人： Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
IPC分类号： H03K17/693 , H03K19/173 , H03K19/20
CPC分类号： H03K17/693 , H03K19/1731
摘要： A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.
摘要翻译： 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。
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公开(公告)号：US06593776B2
公开(公告)日：2003-07-15
申请号：US09922434
申请日：2001-08-03
申请人： Sudarshan Kumar , Gaurav Mehta , Vivek Joshi
发明人： Sudarshan Kumar , Gaurav Mehta , Vivek Joshi
IPC分类号： H03K1994
CPC分类号： G11C8/10
摘要： A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
摘要翻译： 解码器包括多个解码门，每个解码门提供解码输出信号的一位。 至少两个解码门共享晶体管。 根据一个方面，多个解码门中的每一个是偏斜门。
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公开(公告)号：US06351151B2
公开(公告)日：2002-02-26
申请号：US09909104
申请日：2001-07-18
申请人： Sudarshan Kumar , Wenjie Jiang
发明人： Sudarshan Kumar , Wenjie Jiang
IPC分类号： H03K19096
CPC分类号： H03K19/00338 , H03K19/096
摘要： A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.
摘要翻译： 一种降低动态电路软错误的技术。 对于一个实施例，动态电路包括具有输出节点的动态逻辑门，在该输出节点检测逻辑门的逻辑输出值。 耦合到输出节点的保持器电路被配置为通过增加输出节点处的临界电荷来硬化动态电路。
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10.发明授权Method and apparatus to limit current-change induced voltage changes in a microcircuit 失效限制微电路中电流变化感应电压变化的方法和装置公开(公告)号：US07685451B2
公开(公告)日：2010-03-23
申请号：US10327441
申请日：2002-12-20
申请人： James S. Burns , Kenneth D. Shoemaker , Sudarshan Kumar , Tom E. Wang , David J. Ayers , Vivek Tiwari
发明人： James S. Burns , Kenneth D. Shoemaker , Sudarshan Kumar , Tom E. Wang , David J. Ayers , Vivek Tiwari
IPC分类号： G06F1/26
CPC分类号： G06F1/305
摘要： A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.
摘要翻译： 公开了一种用于补偿电流变化感应电压变化的方法和装置。 在一个实施例中，耦合到指令流水线的数字节流单元可以生成补偿电流信号，然后可以使虚拟负载消耗补偿电流。 在另一个实施例中，响应于时钟频率变化的计数器可产生斜坡电流信号，然后可以使虚拟负载消耗对应于斜坡电流信号的电流。
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