公开(公告)号：US08580648B2

公开(公告)日：2013-11-12

申请号：US13035342

申请日：2011-02-25

申请人： Suk-Hun Choi ,  Kyung-Hyun Kim ,  Chang-Sup Mun ,  Sung-Jun Kim ,  Jin-I Lee

发明人： Suk-Hun Choi ,  Kyung-Hyun Kim ,  Chang-Sup Mun ,  Sung-Jun Kim ,  Jin-I Lee

IPC分类号： H01L29/92

CPC分类号： H01L27/10852 ,  H01G4/33 ,  H01L27/10894 ,  H01L28/91

摘要： A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.

摘要翻译： 电容器包括具有开口的绝缘层，具有导电图案的电极结构，电介质层和上部电极的物体或基板。 电极结构可以具有包括金属的第一导电图案和包括从第一导电图案产生的金属氧化物的第二导电图案。 第一导电图案可以填充开口并且可以突出在绝缘层上。 第二导电图案可以从第一导电图案延伸。 电极结构可以另外包括设置在第二导电图案上的第三导电图案。 包括电极结构的电容器可以确保改进的结构稳定性和电特性。

公开(公告)号：US09997534B2

公开(公告)日：2018-06-12

申请号：US15155732

申请日：2016-05-16

申请人： Yong-Hoon Son ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Jong-Heun Lim ,  Won-Bong Jung ,  Kohji Kanamori

发明人： Yong-Hoon Son ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Jong-Heun Lim ,  Won-Bong Jung ,  Kohji Kanamori

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/528

摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

公开(公告)号：US10079203B2

公开(公告)日：2018-09-18

申请号：US15271605

申请日：2016-09-21

申请人： Yong-Hoon Son ,  Cha-Dong Yeo ,  Han-Mei Choi ,  Kyung-Hyun Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

发明人： Yong-Hoon Son ,  Cha-Dong Yeo ,  Han-Mei Choi ,  Kyung-Hyun Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC分类号： H01L23/522 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/1157

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

公开(公告)号：US10559580B2

公开(公告)日：2020-02-11

申请号：US15247602

申请日：2016-08-25

申请人： Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Wonbong Jung

发明人： Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Wonbong Jung

IPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

摘要： A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.