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    Semiconductor Memory Devices
    2.
    发明申请
    Semiconductor Memory Devices 审中-公开

    公开(公告)号：US20170098656A1

    公开(公告)日：2017-04-06

    申请号：US15247602

    申请日：2016-08-25

    申请人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

    发明人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

    IPC分类号： H01L27/115 ,  G11C16/04

    摘要： A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

    Semiconductor memory devices and methods of forming the same
    6.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US08592873B2

    公开(公告)日：2013-11-26

    申请号：US13167858

    申请日：2011-06-24

    申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

    摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

    摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

    Semiconductor devices and methods for fabricating the same
    7.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08482049B2

    公开(公告)日：2013-07-09

    申请号：US12968389

    申请日：2010-12-15

    申请人： Yong-Hoon Son ,  Seungjae Baik ,  Jaehun Jeong ,  Kihun Hwang

    发明人： Yong-Hoon Son ,  Seungjae Baik ,  Jaehun Jeong ,  Kihun Hwang

    IPC分类号： H01L29/76

    CPC分类号： G11C16/0483 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7926

    摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 多个层间电介质层位于基板上。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。 半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。 垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。 垂直通道具有内侧壁。 在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

    Method of manufacturing vertical semiconductor device
    8.
    发明授权
    Method of manufacturing vertical semiconductor device 有权
    垂直半导体器件制造方法

    公开(公告)号：US08455316B2

    公开(公告)日：2013-06-04

    申请号：US13325189

    申请日：2011-12-14

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

    摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

    摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

    Methods of manufacturing rewriteable three-dimensional semiconductor memory devices
    9.
    发明授权
    Methods of manufacturing rewriteable three-dimensional semiconductor memory devices 有权
    制造可重写三维半导体存储器件的方法

    公开(公告)号：US08450176B2

    公开(公告)日：2013-05-28

    申请号：US12968595

    申请日：2010-12-15

    申请人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

    发明人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

    摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

    摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。 这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面 其中的陷阱密度。 该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。 也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。