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16 条记录 (耗时 0.03 秒)

    Circuit and Method of Reducing Pop-up Noise in a Digital Amplifier
    4.
    发明申请
    Circuit and Method of Reducing Pop-up Noise in a Digital Amplifier 有权
    降低数字放大器弹出噪声的电路和方法

    公开(公告)号：US20080089532A1

    公开(公告)日：2008-04-17

    申请号：US11873179

    申请日：2007-10-16

    申请人： Soo-Hyoung Lee ,  Wang-Seup Yeum ,  Yong-Jin Cho ,  In-Bock Lee

    发明人： Soo-Hyoung Lee ,  Wang-Seup Yeum ,  Yong-Jin Cho ,  In-Bock Lee

    IPC分类号： H04B15/00

    CPC分类号： H03F3/217 ,  H03F1/305 ,  H03F2200/03 ,  H03F2200/351 ,  H03K17/162

    摘要： A circuit of reducing a pop-up noise in a digital amplifier includes a switch unit and a switch signal generator. The switch unit is coupled in parallel to an output load between an output node of the digital amplifier and a reference node. The switch unit controls a current flowing through the output load by forming a conduction path between the output node and the reference node in response to a switch signal. The switch signal generator generates the switch signal in response to a switch control signal indicating a power-on or a power-off. The pop-up noise is reduced by the conduction path that is formed when the digital amplifier is powered on or off.

    摘要翻译： 减少数字放大器中的弹出噪声的电路包括开关单元和开关信号发生器。 开关单元与数字放大器的输出节点与参考节点之间的输出负载并联耦合。 开关单元响应于开关信号，在输出节点和参考节点之间形成传导路径来控制流过输出负载的电流。 开关信号发生器响应于指示电源接通或断电的开关控制信号而产生开关信号。 通过在数字放大器通电或关闭时形成的传导路径来减小弹出式噪声。

    Crossing input signal modulator
    5.
    发明授权
    Crossing input signal modulator 有权
    交叉输入信号调制器

    公开(公告)号：US08169244B2

    公开(公告)日：2012-05-01

    申请号：US12867338

    申请日：2009-02-09

    申请人： Soo-Hyoung Lee ,  Jae-Young Shin

    发明人： Soo-Hyoung Lee ,  Jae-Young Shin

    IPC分类号： H03K17/92

    CPC分类号： H03K7/08 ,  H03F3/217

    摘要： The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first-order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals. This configuration allows cross-coupling of the inputs from two integrators to generate an accurate differential pulse width modulation (PWM) single, and enables optimization of the IC implementation by adopting a feedback system that features a simplified implementation and minimal application area.

    摘要翻译： 本发明涉及一种脉冲宽度调制器，更具体地涉及交叉耦合的脉冲宽度调制器。 根据本发明的交叉输入信号调制器包括：正路径块，其包括用于在第一输入和输出信号中执行反馈信号的一阶积分的第一积分器，然后将一阶积分信号发送到第二积分器 以及第二积分器，用于执行来自第一积分器的信号和第二输入信号的二次积分，然后发送二阶积分信号; 以及负路径块，其包括用于执行第二输入中的反馈信号的一级积分的第三积分器和来自第三积分器和第一输入信号的信号的积分，然后发送二阶积分信号 。 该配置允许来自两个积分器的输入的交叉耦合以产生精确的差分脉冲宽度调制（PWM）单个，并且通过采用具有简化实现和最小应用面积的反馈系统来实现IC实现的优化。

    Synchronizing circuits and methods for parallel path analog-to-digital converters
    7.
    发明授权
    Synchronizing circuits and methods for parallel path analog-to-digital converters 失效
    并行路径模数转换器的同步电路和方法

    公开(公告)号：US06784821B1

    公开(公告)日：2004-08-31

    申请号：US10689435

    申请日：2003-10-20

    申请人： Soo-Hyoung Lee

    发明人： Soo-Hyoung Lee

    IPC分类号： H03M112

    CPC分类号： H03M1/0624 ,  H03M1/0836 ,  H03M1/141 ,  H03M1/203 ,  H03M1/368

    摘要： An Analog-to-Digital (A/D) converter includes signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal. A respective signal path includes a comparator. A synchronizing circuit is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator. A respective signal path also includes a respective decoder that is responsive to a respective comparator and to the clock signal.

    摘要翻译： 模拟数字（A / D）转换器包括响应于模拟输入信号的信号路径，以产生多位数字信号。 相应的信号路径包括比较器。 同步电路响应时钟信号和比较器的输出，以产生施加到相应的比较器的相应延迟的时钟信号。 相应的信号路径还包括响应于相应比较器和时钟信号的相应解码器。

    Circuit and method of reducing pop-up noise in a digital amplifier
    8.
    发明授权
    Circuit and method of reducing pop-up noise in a digital amplifier 有权
    降低数字放大器弹出噪声的电路和方法

    公开(公告)号：US08284953B2

    公开(公告)日：2012-10-09

    申请号：US11873179

    申请日：2007-10-16

    申请人： Soo-Hyoung Lee ,  Wang-Seup Yeum ,  Yong-Jin Cho ,  In-Bock Lee

    发明人： Soo-Hyoung Lee ,  Wang-Seup Yeum ,  Yong-Jin Cho ,  In-Bock Lee

    IPC分类号： H04B15/00 ,  H03G11/00 ,  H04R29/00 ,  H02B1/00 ,  H03F1/14 ,  H03F3/38

    CPC分类号： H03F3/217 ,  H03F1/305 ,  H03F2200/03 ,  H03F2200/351 ,  H03K17/162

    摘要： A circuit of reducing a pop-up noise in a digital amplifier includes a switch unit and a switch signal generator. The switch unit is coupled in parallel to an output load between an output node of the digital amplifier and a reference node. The switch unit controls a current flowing through the output load by forming a conduction path between the output node and the reference node in response to a switch signal. The switch signal generator generates the switch signal in response to a switch control signal indicating a power-on or a power-off. The pop-up noise is reduced by the conduction path that is formed when the digital amplifier is powered on or off.

    摘要翻译： 减少数字放大器中的弹出噪声的电路包括开关单元和开关信号发生器。 开关单元与数字放大器的输出节点和参考节点之间的输出负载并联耦合。 开关单元响应于开关信号，在输出节点和参考节点之间形成传导路径来控制流过输出负载的电流。 开关信号发生器响应于指示电源接通或断电的开关控制信号而产生开关信号。 通过在数字放大器通电或关闭时形成的传导路径来减小弹出式噪声。

    Crossing Input Signal Modulator
    9.
    发明申请
    Crossing Input Signal Modulator 有权
    交叉输入信号调制器

    公开(公告)号：US20100308889A1

    公开(公告)日：2010-12-09

    申请号：US12867338

    申请日：2009-02-09

    申请人： Soo-Hyoung Lee ,  Jae-Young Shin

    发明人： Soo-Hyoung Lee ,  Jae-Young Shin

    IPC分类号： G06G7/18

    CPC分类号： H03K7/08 ,  H03F3/217

    摘要： The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first—order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals. This configuration allows cross-coupling of the inputs from two integrators to generate an accurate differential pulse width modulation (PWM) single, and enables optimization of the IC implementation by adopting a feedback system that features a simplified implementation and minimal application area.

    摘要翻译： 本发明涉及一种脉冲宽度调制器，更具体地涉及交叉耦合的脉冲宽度调制器。 根据本发明的交叉输入信号调制器包括：正路径块，其包括用于在第一输入和输出信号中执行反馈信号的一阶积分的第一积分器，然后将一阶积分信号发送到第二积分器 以及第二积分器，用于执行来自第一积分器的信号和第二输入信号的二次积分，然后发送二阶积分信号; 以及负路径块，其包括用于执行第二输入中的反馈信号的一级积分的第三积分器和来自第三积分器和第一输入信号的信号的积分，然后发送二阶积分信号 。 该配置允许来自两个积分器的输入的交叉耦合以产生精确的差分脉冲宽度调制（PWM）单个，并且通过采用具有简化实现和最小应用面积的反馈系统来实现IC实现的优化。

    Multi-phase clock signal generators and methods of generating multi-phase clock signals
    10.
    发明申请
    Multi-phase clock signal generators and methods of generating multi-phase clock signals 失效
    多相时钟信号发生器和产生多相时钟信号的方法

    公开(公告)号：US20050040875A1

    公开(公告)日：2005-02-24

    申请号：US10835308

    申请日：2004-04-29

    申请人： Soo-Hyoung Lee

    发明人： Soo-Hyoung Lee

    IPC分类号： H03K5/15 ,  H03K5/151 ,  H03K5/156 ,  H03L7/06

    CPC分类号： H03K5/1565 ,  H03K5/1515

    摘要： A multi-phase clock signal generator provides multiple clock signals from an input clock signal, the multiple clock signals being inverted from one another and having substantially the same delay and duty cycle characteristics. Methods of generating multiple clock signals are also provided.

    摘要翻译： 多相时钟信号发生器从输入时钟信号提供多个时钟信号，多个时钟信号彼此反相并具有基本相同的延迟和占空比特性。 还提供了产生多个时钟信号的方法。