-
1.发明授权Processor architecture scheme and instruction set for maximizing available opcodes and address selection modes 失效处理器架构方案和指令集，用于最大化可用的操作码和地址选择模式
公开(公告)号：US5987583A
公开(公告)日：1999-11-16
申请号：US959942
申请日：1997-10-29
申请人： Joseph W. Triece , Sumit K. Mitra
发明人： Joseph W. Triece , Sumit K. Mitra
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/35
摘要： A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.
摘要翻译： 一种允许多个寻址模式同时最大化可用操作码和可寻址寄存器数量的系统。 该系统具有处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码。 该系统具有指令集，该指令集具有多个指令。 每个指令具有多个位，其中多个指令中的每一个中的多个位中的每一个都不是用于实现不同寻址模式的专用位。 多个指令中的每一个能够通过在处理器架构方案中寻址虚拟寄存器地址来实现不同的寻址模式。 由于不需要位来实现不同的寻址模式，所以操作码字段和寄存器地址字段的长度由操作码的数量和用户希望实现的可寻址寄存器的数量来确定。
-
2.发明授权Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor 失效处理器架构方案使用虚拟地址寄存器来实现不同的寻址模式及其方法公开(公告)号：US06192463B1
公开(公告)日：2001-02-20
申请号：US08946426
申请日：1997-10-07
申请人： Sumit K. Mitra , Joseph W. Triece
发明人： Sumit K. Mitra , Joseph W. Triece
IPC分类号： G06F926
CPC分类号： G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
摘要翻译： 一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。 与间接寻址指针相关联的一组虚拟地址寄存器位置被保留在存储器中。 保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。 每个虚拟寄存器地址位置启动间接寻址模式，以在访问时与相关联的间接寻址指针一起使用。
-
3.发明授权Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor 有权处理器架构方案使用虚拟地址寄存器来实现不同的寻址模式及其方法公开(公告)号：US06578139B1
公开(公告)日：2003-06-10
申请号：US09691375
申请日：2000-10-18
申请人： Sumit K. Mitra , Joseph W. Triece
发明人： Sumit K. Mitra , Joseph W. Triece
IPC分类号： G06F922
CPC分类号： G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
摘要翻译： 一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。 与间接寻址指针相关联的一组虚拟地址寄存器位置被保留在存储器中。 保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。 每个虚拟寄存器地址位置启动间接寻址模式，以在访问时与相关联的间接寻址指针一起使用。
-
公开(公告)号：US07203818B2
公开(公告)日：2007-04-10
申请号：US10796771
申请日：2004-03-09
申请人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
发明人： Edward Brian Boles , Rodney Jay Drake , Darrel Ray Johansen , Sumit K. Mitra , Randy Yach , James Grosbach , Joshua M. Conner , Joseph W. Triece
CPC分类号： G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
摘要： A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.
摘要翻译： 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，两个文件寄存器用于一些两个操作数指令。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 因此，提高性能并减少程序内存使用。
-
公开(公告)号：US09208095B2
公开(公告)日：2015-12-08
申请号：US11928242
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.
摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。
-
公开(公告)号：US20100306457A1
公开(公告)日：2010-12-02
申请号：US12776046
申请日：2010-05-07
CPC分类号： H04L12/40013 , H04L12/4135 , H04L49/90 , H04L49/901 , H04L2012/40215
摘要： A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.
摘要翻译： 微控制器具有随机存取存储器和控制器区域网络（CAN）控制器，控制单元接收组合的CAN消息。 控制单元使用组合的CAN消息生成缓冲器描述符表条目，并将缓冲器描述符表条目存储在随机存取存储器中，并且缓冲器描述符表条目至少具有来自CAN消息的消息标识符和加载数据，以及 跟随缓冲区描述符表项。
-
公开(公告)号：US07603601B2
公开(公告)日：2009-10-13
申请号：US11355619
申请日：2006-02-16
申请人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
发明人： Cristian P. Masgras , Michael Pyska , Edward Brian Boles , Joseph W. Triece , Igor Wojewoda , Mei-Ling Chen
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
摘要翻译： 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。 特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。
-
公开(公告)号：US20080147979A1
公开(公告)日：2008-06-19
申请号：US11928242
申请日：2007-10-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.
摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。
-
公开(公告)号：US06563740B2
公开(公告)日：2003-05-13
申请号：US09951280
申请日：2001-09-13
IPC分类号： G11C1134
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/3418 , G11C29/50
摘要： An electronic circuit includes a non-volatile memory on an integrated circuit that has several memory cells. The cells each have a voltage state and a gate. A gate bias circuit on the integrated circuit is coupled to the gates of the memory cells. The gate bias circuit includes at least a read voltage and a margin voltage. A detection circuit on the integrated circuit is coupled to the cells. The detection circuit includes a comparator and a reference voltage. The reference voltage and the voltage state of one of the cells are coupled to the comparator. The detection circuit includes an output generating a signal corresponding to the comparator output. The integrated circuit includes a monitor circuit. The monitor circuit is coupled to the output of the detection circuit and determines whether the voltage state of the cell transitions between application of the read and margin voltages to the gate.
-
10.发明授权Circuit for powering down unused configuration bits to minimize power consumption 有权关闭未使用配置位的电路，以最大限度地降低功耗公开(公告)号：US06230275B1
公开(公告)日：2001-05-08
申请号：US09232053
申请日：1999-01-15
申请人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
发明人： Joseph W. Triece , Rodney Drake , Igor Wojewoda
IPC分类号： G06F126
CPC分类号： G11C5/14 , G11C7/1045 , H03K19/0016
摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.
摘要翻译： 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.017 秒)
