公开(公告)号：US06200880B1

公开(公告)日：2001-03-13

申请号：US09192877

申请日：1998-11-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

摘要翻译： 提供了用于形成用于隔离器件的浅沟槽隔离的方法。 衬底氧化物和掩模层形成在衬底上并被图案化。 在图案化区域之下的衬底内形成沟槽，并且沟槽填充绝缘体以形成绝缘插头，其是浅沟槽隔离。 在整个基板表面上形成介电层以覆盖器件区域和绝缘插头。

公开(公告)号：US06284647B1

公开(公告)日：2001-09-04

申请号：US09216022

申请日：1998-12-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L214163

CPC分类号： H01L21/76229 ,  Y10S438/926

摘要： A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

摘要翻译： 提供了增强化学机械抛光均匀性的方法。 在浅沟槽隔离结构的制造中，在芯片中形成不同积分的有源区域。 通过程序分析，根据电路设计计算芯片中有源区域的积分。 集成度最高的有源区域之一被用作基础，在其他有源区域中形成虚拟台面以调整芯片的集成。

公开(公告)号：US06281081B1

公开(公告)日：2001-08-28

申请号：US09192042

申请日：1998-11-13

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

摘要翻译： 当掺杂NMOS器件的源/漏区时，用于制造浅沟槽隔离结构的离子注入方法将磷离子代替砷离子代入衬底。 或者，在离子注入中使用低能离子来形成NMOS器件的源/漏区。 因此，衬底内的晶体结构的晶格位错减少，并且不需要器件漏电流。

公开(公告)号：US06368971B2

公开(公告)日：2002-04-09

申请号：US09348408

申请日：1999-07-07

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

IPC分类号： H01L21302

CPC分类号： H01L28/91 ,  H01L27/10814

摘要： A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed. The remaining fifth dielectric layer and the fourth dielectric layer are removed.

摘要翻译： 一种制造电容器的底部电极的方法。 衬底具有形成在其上的接触焊盘，在接触焊盘上形成第一电介质层，并且节点接触件穿过第一电介质层并电耦合到接触焊盘。 在第一电介质层和节点接触件上形成第二电介质层。 在第二电介质层上形成第三电介质层。 在第三电介质层上形成第四电介质层。 形成沟槽以穿透第四，第三和第二介电层并暴露节点接触的表面。 在第四电介质层和沟槽的侧壁和底部上形成导电层。 在导电层上形成第五电介质层，其中第五介电层填充沟槽。 去除第五电介质层的一部分和导电层的一部分直到暴露第四电介质层的表面。 去除剩余的第五电介质层和第四电介质层。

公开(公告)号：US06509235B2

公开(公告)日：2003-01-21

申请号：US09764333

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L218232

CPC分类号： H01L27/105 ,  H01L21/82345 ,  H01L27/1052

摘要： The present invention provides a method for forming an embedded memory MOS. The method involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of the semiconductor wafer with a defined memory array area and a periphery circuits region. Then, the undoped polysilicon layer in the memory array area is doped to become a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is applied to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of each MOS in the periphery circuits region and the memory array area. Finally, a lightly doped drain (LDD) of each MOS is formed, as well as a spacer and a source/drain (S/D) adjacent to each gate in the periphery circuits region.

摘要翻译： 本发明提供一种形成嵌入式存储器MOS的方法。 该方法包括首先在具有限定的存储器阵列区域和外围电路区域的半导体晶片的表面上分别形成介电层和未掺杂的多晶硅层。 然后，将存储器阵列区域中未掺杂的多晶硅层掺杂成为掺杂多晶硅层。 此后，在半导体晶片的表面上形成保护层，然后进行第一光刻和蚀刻工艺（PEP），以在存储器阵列区域中的保护层中限定多个栅极图案。 然后，施加第二PEP以蚀刻外围电路区域中的未掺杂多晶硅层和存储器阵列区域中的掺杂多晶硅层，以在外围电路区域和存储器阵列区域中同时形成每个MOS的栅极。 最后，形成每个MOS的轻掺杂漏极（LDD），以及与外围电路区域中的每个栅极相邻的间隔物和源极/漏极（S / D）。

公开(公告)号：US06465364B2

公开(公告)日：2002-10-15

申请号：US09764328

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L21/28518 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

摘要翻译： 本发明提供一种用于形成嵌入式存储器的接触塞的方法。 该方法首先在半导体晶片的限定的存储器阵列区域和外围电路区域上形成多个MOS晶体管。 然后，在存储器阵列区域上形成第一电介质层，并且在第一介电层中形成多个着陆焊盘。 接下来，在半导体晶片的表面上分别形成停止层和第二电介质层。 然后使用PEP工艺在存储器阵列区域和外围电路区域中的第二介电层中形成多个接触插塞孔。 最后，将导电层填充到每个孔中，以在存储器阵列区域和外围电路区域中的原位形成每个接触插塞。

公开(公告)号：US06406968B1

公开(公告)日：2002-06-18

申请号：US09767499

申请日：2001-01-23

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

摘要： A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.

摘要翻译： 一种形成动态随机存取存储器的方法。 提供具有存储单元区域和逻辑电路区域的衬底。 衬底上也具有第一介电层。 存储单元区域中的第一介电层具有位线和节点接​​触，而逻辑电路区域中的第一介电层具有第一金属互连。 中间电介质层形成在第一电介质层上，使得逻辑电路区域中的中间介电层具有与第一金属互连电连接的第二金属互连。 在存储单元区域内的中间介质层中形成电容器。 第二介质层形成在衬底上。 在第二电介质层中形成第三金属互连，使得第三金属互连和第二金属互连电连接。

公开(公告)号：US06248623B1

公开(公告)日：2001-06-19

申请号：US09439170

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L28242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823468 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

摘要： A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.

摘要翻译： 一种制造嵌入式存储器的方法。 衬底具有存储单元区域和逻辑电路区域。 多个第一栅极结构和多个第二栅极结构分别形成在存储单元区域和逻辑电路区域中的衬底上。 第一栅极结构之间的每个空间都小于第二栅极结构之间的间隔。 在每个第一栅极结构的侧壁上并且在每个第二栅极结构的侧壁之上形成第一间隔物。 在由第一间隔物和逻辑电路区域中的第二栅极结构暴露的衬底中形成几个轻掺杂漏极区。 在逻辑电路区域中的每个第一间隔物上形成第二间隔物，同时形成硅化物块以填充存储单元区域中的第一栅极结构之间的空间。 源极/漏极区域形成在由第二间隔物暴露的衬底中，第一间隔物和第二栅极结构在逻辑电路区域中。 在由第二间隔物暴露的衬底上形成硅化物层，在逻辑电路区域中形成第一间隔物和第二栅极结构。

公开(公告)号：US06281067B1

公开(公告)日：2001-08-28

申请号：US09439932

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/10873

摘要： A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

摘要翻译： 用于在DRAM中的字线上形成硅化物层的自对准工艺以及在逻辑器件区域中的晶体管上的硅化物层。 提供了包括存储单元区域和逻辑电路区域的基板。 第一晶体管和第二晶体管形成在衬底上。 第一晶体管形成在逻辑电路区域中，并且包括第一栅极导电层和第一源极/漏极区域。 第二晶体管形成在存储单元区域中，并且包括第二栅极导电层和第二源极/漏极区域。 在第一晶体管和第二晶体管两端形成阻挡层。 去除阻挡层的一部分以暴露第一栅极导电层，第一源极/漏极区域和第二栅极导电层。 剩余的阻挡层仍然覆盖第二源极/漏极区域。 在第一栅极导电层，第一源极/漏极区域和第二栅极导电层上形成金属硅化物层。

公开(公告)号：US06559059B2

公开(公告)日：2003-05-06

申请号：US09764327

申请日：2001-01-19

申请人： Sun-Chieh Chien ,  Chien-Li Kuo

发明人： Sun-Chieh Chien ,  Chien-Li Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

摘要： The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed. Finally, the undoped polysilicon layer is etched to form a plurality of gates in the periphery circuit region, followed by the formation of spacers, sources and drains of each MOS transistors, respectively, in the periphery circuit region.