公开(公告)号：US06284647B1

公开(公告)日：2001-09-04

申请号：US09216022

申请日：1998-12-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L214163

CPC分类号： H01L21/76229 ,  Y10S438/926

摘要： A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.

摘要翻译： 提供了增强化学机械抛光均匀性的方法。 在浅沟槽隔离结构的制造中，在芯片中形成不同积分的有源区域。 通过程序分析，根据电路设计计算芯片中有源区域的积分。 集成度最高的有源区域之一被用作基础，在其他有源区域中形成虚拟台面以调整芯片的集成。

公开(公告)号：US06200880B1

公开(公告)日：2001-03-13

申请号：US09192877

申请日：1998-11-16

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

摘要翻译： 提供了用于形成用于隔离器件的浅沟槽隔离的方法。 衬底氧化物和掩模层形成在衬底上并被图案化。 在图案化区域之下的衬底内形成沟槽，并且沟槽填充绝缘体以形成绝缘插头，其是浅沟槽隔离。 在整个基板表面上形成介电层以覆盖器件区域和绝缘插头。

公开(公告)号：US06281081B1

公开(公告)日：2001-08-28

申请号：US09192042

申请日：1998-11-13

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Tzung-Han Lee ,  Wei-Wu Liao

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： An ion implantation method useful for fabricating shallow trench isolation structureimplants phosphorus ions instead of arsenic ions into a substrate when the source/drain regions of an NMOS device are doped. Alternatively, low energy ions are used in the ion implantation for forming the source/drain regions of an NMOS device. Consequently lattice dislocations of the crystal structure within a substrate is reduced and unwanted device leakage current is eliminated.

摘要翻译： 当掺杂NMOS器件的源/漏区时，用于制造浅沟槽隔离结构的离子注入方法将磷离子代替砷离子代入衬底。 或者，在离子注入中使用低能离子来形成NMOS器件的源/漏区。 因此，衬底内的晶体结构的晶格位错减少，并且不需要器件漏电流。

公开(公告)号：US06368971B2

公开(公告)日：2002-04-09

申请号：US09348408

申请日：1999-07-07

申请人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Chien-Li Kuo ,  Wei-Wu Liao

IPC分类号： H01L21302

CPC分类号： H01L28/91 ,  H01L27/10814

摘要： A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed. The remaining fifth dielectric layer and the fourth dielectric layer are removed.

摘要翻译： 一种制造电容器的底部电极的方法。 衬底具有形成在其上的接触焊盘，在接触焊盘上形成第一电介质层，并且节点接触件穿过第一电介质层并电耦合到接触焊盘。 在第一电介质层和节点接触件上形成第二电介质层。 在第二电介质层上形成第三电介质层。 在第三电介质层上形成第四电介质层。 形成沟槽以穿透第四，第三和第二介电层并暴露节点接触的表面。 在第四电介质层和沟槽的侧壁和底部上形成导电层。 在导电层上形成第五电介质层，其中第五介电层填充沟槽。 去除第五电介质层的一部分和导电层的一部分直到暴露第四电介质层的表面。 去除剩余的第五电介质层和第四电介质层。

公开(公告)号：US06281067B1

公开(公告)日：2001-08-28

申请号：US09439932

申请日：1999-11-12

申请人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

发明人： Sun-Chieh Chien ,  Hal Lee ,  Jhy-Jeng Liu ,  Wei-Wu Liao

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/10873

摘要： A self-aligned process for forming a silicide layer over word lines in DRAM and a silicide layer over transistors in a logic device region. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.

摘要翻译： 用于在DRAM中的字线上形成硅化物层的自对准工艺以及在逻辑器件区域中的晶体管上的硅化物层。 提供了包括存储单元区域和逻辑电路区域的基板。 第一晶体管和第二晶体管形成在衬底上。 第一晶体管形成在逻辑电路区域中，并且包括第一栅极导电层和第一源极/漏极区域。 第二晶体管形成在存储单元区域中，并且包括第二栅极导电层和第二源极/漏极区域。 在第一晶体管和第二晶体管两端形成阻挡层。 去除阻挡层的一部分以暴露第一栅极导电层，第一源极/漏极区域和第二栅极导电层。 剩余的阻挡层仍然覆盖第二源极/漏极区域。 在第一栅极导电层，第一源极/漏极区域和第二栅极导电层上形成金属硅化物层。

公开(公告)号：US06153479A

公开(公告)日：2000-11-28

申请号：US74959

申请日：1998-05-07

申请人： Wei-Wu Liao ,  Andy Chuang ,  Chien-Li Kuo

发明人： Wei-Wu Liao ,  Andy Chuang ,  Chien-Li Kuo

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/461 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of fabricating shallow trench isolation structures. A substrate is provided and a masking layer and an oxide layer are formed respectively on the substrate. The masking layer, the oxide layer and the substrate are defined and an opening is formed within the substrate. A portion of masking layer and the oxide layer are removed and an insulating material is later formed to fill with the opening. The masking layer is removed and the shallow trench isolation structure of this invention is therefore achieved.

摘要翻译： 一种制造浅沟槽隔离结构的方法。 提供基板，并且在基板上分别形成掩模层和氧化物层。 限定掩模层，氧化物层和衬底，并在衬底内形成开口。 去除一部分掩模层和氧化物层，然后形成绝缘材料以填充开口。 去除掩模层，从而实现本发明的浅沟槽隔离结构。

公开(公告)号：US06727180B2

公开(公告)日：2004-04-27

申请号：US09839365

申请日：2001-04-23

申请人： Chien-Li Kuo ,  Wei-Wu Liao

发明人： Chien-Li Kuo ,  Wei-Wu Liao

IPC分类号： H01L21301

CPC分类号： H01L21/76804

摘要： A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.

摘要翻译： 公开了一种形成接触窗的方法。 本发明的基本概念包括在形成接触窗形成之前在表面上形成的覆盖层，并且过涂层的蚀刻速率高于下层的蚀刻速率。 该方法包括以下步骤：首先在晶片表面形成半导体结构。 其次，在表面上形成覆盖层并覆盖这些半导体结构。 第三，在涂层上形成过涂层，其中涂层的蚀刻速率高于涂层的蚀刻速率。 最后，形成具有向外缠绕形状的接触窗。 因此，本发明形成的接触窗比常规方法形成的接触窗更容易填充材料。 此外，由于接触窗宽度不明显增加，本发明对深亚微米制造更有利。

公开(公告)号：US20050030079A1

公开(公告)日：2005-02-10

申请号：US10708104

申请日：2004-02-10

申请人： Wei-Ming Ku ,  Yu-Ming Hsu ,  Wei-Wu Liao

发明人： Wei-Ming Ku ,  Yu-Ming Hsu ,  Wei-Wu Liao

IPC分类号： G11C7/12 ,  H03H11/26 ,  H03K5/00 ,  H03K5/08 ,  H03K5/13

CPC分类号： H03K5/13 ,  H03K5/082 ,  H03K2005/00156 ,  H03K2005/00195

摘要： A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator for providing a reference voltage, a differential amplifier, and a feedback control module. The current generator starts to provide a charging current to the storage unit when the input signal changes level, such that an output charging voltage of the storages unit is gradually charged to reach the reference voltage. The feedback control module is capable of dynamically decreasing the charging current provided to the storage unit as the charging voltage is approaching the reference voltage, and the amplifier will change the level of the output voltage when the charging voltage reaches the reference voltage.

摘要翻译： 一种用于提供更长延迟时间的延迟电路和相关装置，使得当输入信号的电平改变时，在预定延迟时间之后，输出信号的电平相应地改变。 延迟电路具有存储单元，电流发生器，用于提供参考电压的电压发生器，差分放大器和反馈控制模块。 当输入信号改变电平时，电流发生器开始向存储单元提供充电电流，使得存储单元的输出充电电压逐渐被充电以达到参考电压。 当充电电压接近参考电压时，反馈控制模块能够动态地减小提供给存储单元的充电电流，并且当充电电压达到参考电压时，放大器将改变输出电压的电平。

公开(公告)号：US06627551B2

公开(公告)日：2003-09-30

申请号：US09874530

申请日：2001-06-06

申请人： Wei-Wu Liao

发明人： Wei-Wu Liao

IPC分类号： H01L21302

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L27/10852 ,  H01L27/10894

摘要： This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.

公开(公告)号：US08867279B2

公开(公告)日：2014-10-21

申请号：US13530083

申请日：2012-06-21

申请人： Yu-Hsiung Tsai ,  Wei-Wu Liao

发明人： Yu-Hsiung Tsai ,  Wei-Wu Liao

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/26

摘要： The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.

摘要翻译： 本发明提供了一种包括至少一个闪速存储器阵列块和感测放大模块的闪存装置。 闪存阵列块包括N个存储列，N个参考字线单元单元和参考存储列，其中N是正整数。 设置在每个存储列中的每个参考字线单元单元，其中，参考字线单元单元还耦合到参考字线和虚拟字线。 参考存储列包括多个参考位线单元，参考字线和虚拟字线，耦合到参考字线的参考位线单元之一耦合到参考位线。 感测放大模块比较来自位线之一和相应的参考位线的电流以产生至少一个感测结果。