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    Channel layers and semiconductor devices including the same
    2.
    发明申请
    Channel layers and semiconductor devices including the same 有权
    通道层和包括其的半导体器件

    公开(公告)号：US20100006834A1

    公开(公告)日：2010-01-14

    申请号：US12458491

    申请日：2009-07-14

    申请人： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    发明人： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    IPC分类号： H01L29/26 ,  H01L29/786

    CPC分类号： H01L29/7869 ,  H01L29/78696

    摘要： Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

    摘要翻译： 公开了包括沟道层的通道层和半导体器件。 沟道层可以包括多层结构。 形成沟道层的层可具有不同的载流子迁移率和/或载流子密度。 沟道层可以具有双层结构，其包括可由不同氧化物形成的第一层和第二层。 晶体管的特性可以根据用于形成沟道层的材料和/或其厚度而变化。

    Transistor and method of manufacturing the same
    3.
    发明申请
    Transistor and method of manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号：US20090224238A1

    公开(公告)日：2009-09-10

    申请号：US12289252

    申请日：2008-10-23

    申请人： Sun-il Kim ,  Young-soo Park ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    发明人： Sun-il Kim ,  Young-soo Park ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/7869

    摘要： A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

    摘要翻译： 根据示例实施例的晶体管可以包括沟道层，分别接触沟道层的端部的源极和漏极，与沟道层分离的栅电极，介于沟道层和栅电极之间的栅极绝缘层和/ 或形成在沟道层和栅极绝缘层之间的插入层。 插入层可以具有与沟道层不同的功函数。

    Stacked memory device and method thereof
    5.
    发明授权
    Stacked memory device and method thereof 有权
    堆叠式存储器件及其方法

    公开(公告)号：US08547719B2

    公开(公告)日：2013-10-01

    申请号：US12588275

    申请日：2009-10-09

    申请人： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    发明人： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    IPC分类号： G11C5/02

    CPC分类号： G11C5/02 ,  G11C5/143 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71

    摘要： A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

    摘要翻译： 堆叠存储器件包括多个存储器层，其中多个存储器层中的至少一个堆叠在多个存储器层中的另一个上，并且每个存储器层包括存储器单元阵列，第一有源电路单元配置 将至少一个存储器单元的地址信息分类并处理为垂直地址信息和水平地址信息，以及至少一个第二有源电路单元，配置为基于处理的信号为存储器单元中的至少一个生成存储器选择信号 由第一有源电路单元。

    Channel layers and semiconductor devices including the same
    6.
    发明授权
    Channel layers and semiconductor devices including the same 有权
    通道层和包括其的半导体器件

    公开(公告)号：US08232551B2

    公开(公告)日：2012-07-31

    申请号：US12458491

    申请日：2009-07-14

    申请人： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    发明人： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

    IPC分类号： H01L29/26

    CPC分类号： H01L29/7869 ,  H01L29/78696

    摘要： Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

    摘要翻译： 公开了包括沟道层的通道层和半导体器件。 沟道层可以包括多层结构。 形成沟道层的层可具有不同的载流子迁移率和/或载流子密度。 沟道层可以具有双层结构，其包括可由不同氧化物形成的第一层和第二层。 晶体管的特性可以根据用于形成沟道层的材料和/或其厚度而变化。

    Stacked memory device and method thereof
    8.
    发明申请
    Stacked memory device and method thereof 有权
    堆叠式存储器件及其方法

    公开(公告)号：US20100091541A1

    公开(公告)日：2010-04-15

    申请号：US12588275

    申请日：2009-10-09

    申请人： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    发明人： Jae-chul Park ,  Kee-won Kwon ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

    IPC分类号： G11C5/02 ,  G11C8/10 ,  G11C11/00 ,  G11C7/00

    CPC分类号： G11C5/02 ,  G11C5/143 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0023 ,  G11C2213/71

    摘要： A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

    摘要翻译： 堆叠存储器件包括多个存储器层，其中多个存储器层中的至少一个堆叠在多个存储器层中的另一个上，并且每个存储器层包括存储器单元阵列，第一有源电路单元配置 将至少一个存储器单元的地址信息分类并处理为垂直地址信息和水平地址信息，以及至少一个第二有源电路单元，配置为基于处理的信号为存储器单元中的至少一个生成存储器选择信号 由第一有源电路单元。