公开(公告)号：US20070143031A1

公开(公告)日：2007-06-21

申请号：US11702987

申请日：2007-02-06

Applicant: Yang-Suk Kim ,  Jung-Uk Hur ,  Sung-Geun Lee

Inventor： Yang-Suk Kim ,  Jung-Uk Hur ,  Sung-Geun Lee

IPC: G06F19/00

CPC classification number: G16B50/00 ,  G16B25/00 ,  G16B40/00

Abstract: Disclosed is a system for analyzing a bio chip using Gene Ontology (hereinafter referred to “GO”) and a method thereof. According to a preferred embodiment of the present invention, it is provided a system for analyzing a bio chip comprising: a GO (gene ontology) term assigning part for receiving a statistical clustering data obtained from empirical results of the bio chip, and assigning relevant GO terms to every gene contained in each cluster; a GO code converting part for converting the GO terms assigned by the GO term assigning part to the genes into GO codes, the GO code comprising a group of predetermined numbers; and a biological meaning extracting part for calculating pseudo distances between one of GO terms on GO tree structure contained in a predetermined group and the GO terms corresponding to the genes contained in the cluster, and calculating at least one of average pseudo distance or maximum pseudo distance of the calculated pseudo distances, and calculating at least one of average pseudo distances or maximum pseudo distances for all GO terms included on GO tree structure in the predetermined group and the GO terms corresponding to the genes contained in the cluster, and determining an optimum GO term matching with the cluster.

Abstract translation: 公开了使用基因本体（以下称为“GO”）分析生物芯片的方法及其方法。 根据本发明的优选实施例，提供了一种用于分析生物芯片的系统，包括：GO（基因本体）术语分配部分，用于接收从生物芯片的经验结果获得的统计聚类数据，并分配相关的GO 对每个簇中每个基因的术语; GO代码转换部分，用于将由GO条目分配部分分配给GO基因的GO条目转换成GO代码，GO代码包括一组预定数量; 以及用于计算包含在预定组中的GO树结构上的GO项之一和与所述簇中包含的基因相对应的GO项之间的伪距离的生物意义提取部分，并且计算平均伪距离或最大伪距离 的计算的伪距离，并且计算包含在预定组中的GO树结构上的所有GO项的平均伪距离或最大伪距离中的至少一个，以及对应于簇中包含的基因的GO项，并且确定最佳GO 与群集的长期匹配。

公开(公告)号：US20060234244A1

公开(公告)日：2006-10-19

申请号：US10579504

申请日：2004-08-23

Applicant: Yang-Suk Kim ,  Jung-Uk Hur ,  Sung-Geun Lee

Inventor： Yang-Suk Kim ,  Jung-Uk Hur ,  Sung-Geun Lee

IPC: C12Q1/68 ,  G06F19/00

CPC classification number: G16B50/00 ,  G16B25/00 ,  G16B40/00

Abstract: Disclosed is a system for analyzing a bio chip using Gene Ontology(hereinafter referred to “GO”) and a method thereof. According to a preferred embodiment of the present invention, it is provided a system for analyzing a bio chip comprising: a GO(gene ontology) term assigning part for receiving a statistical clustering data obtained from empirical results of the bio chip, and assigning relevant GO terms to every gene contained in each cluster; a GO code converting part for converting the GO terms assigned by the GO term assigning part to the genes into GO codes, the GO code comprising a group of predetermined numbers; and a biological meaning extracting part for calculating pseudo distances between one of GO terms on GO tree structure contained in a predetermined group and the GO terms corresponding to the genes contained in the cluster, and calculating at least one of average pseudo distance or maximum pseudo distance of the calculated pseudo distances, and calculating at least one of average pseudo distances or maximum pseudo distances for all GO terms included on GO tree structure in the predetermined group and the GO terms corresponding to the genes contained in the cluster, and determining an optimum GO term matching with the cluster.

Abstract translation: 公开了使用基因本体（以下称为“GO”）分析生物芯片的方法及其方法。 根据本发明的优选实施例，提供了一种用于分析生物芯片的系统，包括：GO（基因本体）术语分配部分，用于接收从生物芯片的经验结果获得的统计聚类数据，并分配相关的GO 对每个簇中每个基因的术语; GO代码转换部分，用于将由GO条目分配部分分配给GO基因的GO条目转换成GO代码，GO代码包括一组预定数量; 以及用于计算包含在预定组中的GO树结构上的GO项之一和与所述簇中包含的基因相对应的GO项之间的伪距离的生物意义提取部分，并且计算平均伪距离或最大伪距离 的计算的伪距离，并且计算包含在预定组中的GO树结构上的所有GO项的平均伪距离或最大伪距离中的至少一个，以及对应于簇中包含的基因的GO项，并且确定最佳GO 与群集的长期匹配。

公开(公告)号：US06222894B1

公开(公告)日：2001-04-24

申请号：US08990486

申请日：1997-12-18

Applicant: Sung-Geun Lee

Inventor： Sung-Geun Lee

IPC: H03K514

CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814

Abstract: A digital delay locked loop for a synchronous semiconductor memory device reduces power consumption by disabling the stages of the delay locked loop that are not required for generating an internal clock signal that is synchronized with an external system clock signal. The delay locked loop includes a first synchronous delay line formed from a plurality of serially connected unit delayers, a second synchronous delay line formed from a second plurality of serially connected unit delayers, a plurality of phase detectors arranged in successive order to compare the external clock signal to the plurality of delayed clock signals and generate a plurality of enable signals, and a plurality of switches arranged in successive order to select a delayed clock signal from the second delay line as an internal clock signal. Each stage includes one of the unit delayers in the first delay line, one of the unit delayers in the second delay line, one of the phase detectors, and one of the switches. Each of the phase detectors generates a carry signal if the clock signal from its stage is synchronized with the system clock or if it is downstream from the stage that is synchronized. The carry signal from each stage is coupled to the next successive stage. Each of the stages has one or more operation cutting circuits to disable the stage responsive to an active carry signal from the previous stage. The operation cutting circuits can be included in the phase detectors and the unit delayers in each stage to disable inverters in the unit delayers and latches in the phase detectors to conserve power in stages that are not necessary for generating the internal clock signal.

Abstract translation: 用于同步半导体存储器件的数字延迟锁定环通过禁止不产生与外部系统时钟信号同步的内部时钟信号所需的延迟锁定环路的级来降低功耗。 所述延迟锁定环路包括由多个串联连接的单位延迟器形成的第一同步延迟线，由第二多个串联单元延迟器形成的第二同步延迟线，多个相位检测器，以相继的顺序排列以比较外部时钟 信号到多个延迟的时钟信号并产生多个使能信号，以及多个开关按顺序排列，以选择来自第二延迟线的延迟的时钟信号作为内部时钟信号。 每个级包括第一延迟线中的单位延迟器之一，第二延迟线中的单位延迟器之一，相位检测器之一和开关之一。 如果来自其级的时钟信号与系统时钟同步或者是从同步的级的下游，则每个相位检测器产生进位信号。 来自每个级的进位信号被耦合到下一个连续级。 每个级具有一个或多个操作切割电路，以响应于来自前一级的有效进位信号来禁用级。 操作切割电路可以包括在每个级中的相位检测器和单元延迟器中，以禁止相位检测器中的单位延迟器和锁存器中的反相器，以节省产生内部时钟信号所必需的功率。

公开(公告)号：US6147527A

公开(公告)日：2000-11-14

申请号：US136871

申请日：1998-08-19

Applicant: Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

Inventor： Jung-Bae Lee ,  Sung-Geun Lee ,  Jing-Man Han

IPC: G11C11/407 ,  G06F1/04 ,  G06F1/10 ,  G11C7/22 ,  G11C11/34 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H04L7/033 ,  H03K5/14

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/133 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/087 ,  H04L7/0337

Abstract: An internal clock generator including a switching controller interposed between a digital delay locked loop and an externally generated clock signal. The switching controller reduces current consumptions starting from a next cycle when an external clock and an internal clock are in phase. Further, when the external clock and the internal clock are in phase, driving of the unnecessary elements is suppressed, thereby reducing the current consumption in the internal clock generator.

Abstract translation: 内部时钟发生器，其包括插入在数字延迟锁定环和外部产生的时钟信号之间的开关控制器。 当外部时钟和内部时钟同相时，开关控制器可以从下一个周期开始降低电流消耗。 此外，当外部时钟和内部时钟同相时，不必要元件的驱动被抑制，从而降低了内部时钟发生器的电流消耗。