公开(公告)号：US20050002241A1

公开(公告)日：2005-01-06

申请号：US10837610

申请日：2004-05-04

申请人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

发明人： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

IPC分类号： G06F12/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06

CPC分类号： G06F13/4086

摘要： A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

摘要翻译： 存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。 该系统还包括连接到存储器总线之间的存储器控​​制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。 虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

公开(公告)号：US20050185439A1

公开(公告)日：2005-08-25

申请号：US11064671

申请日：2005-02-24

申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

IPC分类号： G06F12/00 ,  G11C5/06 ,  G11C11/401 ,  H05K1/18

CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

公开(公告)号：US07106613B2

公开(公告)日：2006-09-12

申请号：US11064671

申请日：2005-02-24

申请人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

发明人： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

摘要： The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

摘要翻译： 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

公开(公告)号：US07390973B2

公开(公告)日：2008-06-24

申请号：US11357500

申请日：2006-02-17

申请人： Chil-Nam Yoon ,  Kwang-Seop Kim ,  Do-Hyung Kim ,  Jae-Jun Lee ,  Ki-Hyun Ko

发明人： Chil-Nam Yoon ,  Kwang-Seop Kim ,  Do-Hyung Kim ,  Jae-Jun Lee ,  Ki-Hyun Ko

IPC分类号： H05K1/16

CPC分类号： H05K1/181 ,  G11C5/025 ,  G11C5/04 ,  H05K1/112 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611 ,  Y10T29/49128 ,  Y10T29/49155

摘要： The pesent invention discloses a memory module and a signal line arrangement method thereof. The memory module includes memory chips mounted on both sidees in a mirror form; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sodes which same signal applying balls of the memory chips contact in the mirror form, wherein a via is formed at a location close to the same signal applying contact pad of one side among the same signal applying contact pads arranged on both sides in the mirror form, the via connecting the other side to the signal line of one side, and a signal transmitted from the other side is connected to a contact junction, the contact junction is connected to the same signal applying contact pad of the other side, the contact junction is connected to the via of the other side, and the via of one side is connected to the same signal applying contact pad of one side.

摘要翻译： 本发明公开了一种存储模块及其信号线排列方法。 存储器模块包括以镜子形式安装在两侧的存储器芯片; 以及具有相同信号的印刷电路板（PCB），其施加布置在两个信号线上的接触焊盘，所述存储器芯片的相同信号施加球以镜子形式接触，其中通孔形成在接近相同信号的位置处，施加接触焊盘 在相同的信号中，以镜面形式设置在两侧的接触焊盘的一侧，将另一侧连接到一侧的信号线的通孔，并且从另一侧传输的信号连接到接触接点，接触接点 连接到另一侧的相同信号施加接触焊盘，接触点连接到另一侧的通孔，并且一侧的通孔连接到施加一侧接触焊盘的相同信号。

公开(公告)号：US20060207788A1

公开(公告)日：2006-09-21

申请号：US11357500

申请日：2006-02-17

申请人： Chil-Nam Yoon ,  Kwang-Seop Kim ,  Do-Hyung Kim ,  Jae-Jun Lee ,  Ki-Hyun Ko

发明人： Chil-Nam Yoon ,  Kwang-Seop Kim ,  Do-Hyung Kim ,  Jae-Jun Lee ,  Ki-Hyun Ko

IPC分类号： H05K7/06

CPC分类号： H05K1/181 ,  G11C5/025 ,  G11C5/04 ,  H05K1/112 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611 ,  Y10T29/49128 ,  Y10T29/49155

摘要： In a memory module and a signal line arrangement method thereof, the memory module comprises: memory chips mounted on both sides of the module in a mirrored configuration; and a printed circuit board (PCB) having same signal applying contact pads arranged on both sides in contact with same signal applying balls of the memory chips in the mirrored configuration, the PCB including a via at a location proximal to the same signal applying contact pad of one side of the PCB among the same signal applying contact pads arranged on both sides in the mirrored configuration, the via connecting an other side of the PCB to the one side of the PCB, and a contact junction connected to the same signal applying contact pad of the other side of the PCB, the contact junction being connected to the via of the other side of the PCB, and the via of the one side of the PCB being connected to the same signal applying contact pad of the one side of the PCB, the contact junction connected to a signal terminal from the other side of the PCB.

摘要翻译： 在存储器模块及其信号线布置方法中，存储器模块包括：以镜像配置安装在模块两侧的存储器芯片; 以及具有相同信号的印刷电路板（PCB），其施加布置在两侧的接触焊盘，以与镜像配置中的存储器芯片的相同信号施加球接触，PCB包括位于相邻信号施加接触垫 在布置在镜面配置两侧的相同信号施加接触垫中的PCB的一侧，通孔将PCB的另一侧连接到PCB的一侧，以及连接到相同信号的接触点施加接触 PCB的另一侧的焊盘，接触点连接到PCB的另一侧的通孔，并且PCB的一侧的通孔连接到施加与该PCB的一侧的接触焊盘相同的信号 PCB，接触点从PCB的另一侧连接到信号端子。

公开(公告)号：US07215561B2

公开(公告)日：2007-05-08

申请号：US10644735

申请日：2003-08-21

申请人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

发明人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

IPC分类号： G11C5/00 ,  G11C8/00

CPC分类号： G06F13/4234 ,  Y02D10/14 ,  Y02D10/151

摘要： The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory module groups are connected to the N system data buses and respectively have N memory modules. In each of the first through P-th memory module groups, a different one of the N system data buses is connected to each of the N memory modules, and each of the N system data buses has a data bus width of M/N bits. The first through P-th memory module groups are operated in response to first through P-th corresponding chip select signals. M is the bit-width of an entire system data bus of the semiconductor memory system. The N system data buses are wired such that data transmission times are the same from each N memory modules that operate in response to the same chip select signal to the memory controller.

摘要翻译： 半导体存储器系统包括存储器控制器，N个系统数据总线以及第一到第P个存储器模块组。 N个系统数据总线连接到存储器控制器，并且分别具有M / N位的宽度。 第一至第P存储器模块组连接到N个系统数据总线，并分别具有N个存储器模块。 在第一到第P存储器模块组中的每一个中，N个系统数据总线中的不同的一个连接到N个存储器模块中的每一个，并且N个系统数据总线中的每一个具有M / N位的数据总线宽度 。 响应于第一至第P对应的芯片选择信号操作第一到第P个存储器模块组。 M是半导体存储器系统的整个系统数据总线的位宽。 N系统数据总线被布线，使得数据传输时间与从存储器控制器的相同芯片选择信号响应的每个N个存储器模块相同。

公开(公告)号：US07180327B2

公开(公告)日：2007-02-20

申请号：US10997406

申请日：2004-11-24

申请人： Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

发明人： Byung-Se So ,  Jeong-Hyeon Cho ,  Jae-Jun Lee

IPC分类号： H03K17/16 ,  G11C8/12

CPC分类号： H04L25/0278 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1084

摘要： For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.

摘要翻译： 对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。 激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。 用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

公开(公告)号：US06828819B2

公开(公告)日：2004-12-07

申请号：US10353924

申请日：2003-01-30

申请人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

发明人： Myun-Joo Park ,  Byung-Se So ,  Jae-Jun Lee

IPC分类号： H03K1716

CPC分类号： G06F13/4086 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H05K1/023 ,  H05K1/14

摘要： A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.

摘要翻译： 存储器系统包括安装在电路板上的芯片组，以及分别安装在电路板上的第一和第二存储器模块连接器。 第一和第二存储器模块分别插入到第一和第二存储器模块连接器中。 存储器系统还包括连接到芯片组的总线和第一和第二存储器模块连接器，以便产生分支点。 第一和第二存储器模块中的每一个包括经由短截线和短截线电阻连接到总线的至少一个存储器件。 公交车的阻力小于短线的阻力。

公开(公告)号：US07350120B2

公开(公告)日：2008-03-25

申请号：US10833322

申请日：2004-04-28

申请人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

发明人： Jeong-Hyeon Cho ,  Byung-Se So ,  Jae-Jun Lee

IPC分类号： G11C29/00 ,  G01R31/02

CPC分类号： G11C29/48 ,  G11C2029/5602 ,  G11C2029/5606

摘要： A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.

摘要翻译： 缓冲存储器模块包括安装的缓冲电路和安装在板的第一表面上的多个存储器件，存储器件电连接到缓冲电路。 存储器模块还包括位于板的第二表面上并电连接到缓冲电路的多个测试焊盘。

公开(公告)号：US07254675B2

公开(公告)日：2007-08-07

申请号：US10629866

申请日：2003-07-30

申请人： Jae-Jun Lee ,  Byung-Se So ,  Myun-Joo Park

发明人： Jae-Jun Lee ,  Byung-Se So ,  Myun-Joo Park

IPC分类号： G06F12/00

CPC分类号： G06F13/4086

摘要： A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal, and a dual in-line memory module (DIMM) which contains two memory devices and a signal transmission line connected between the two memory devices and a connection terminal. A length of the signal transmission line of the SIMM is longer than a length of the signal transmission line of the DIMM. The load of the memory device of the SIMM is less than the load of memory devices of the DIMM, and the longer length of the signal transmission line of the SIMM increases a signal delay time of the SIMM to compensate for the different loads of the SIMM and DIMM memory devices. The longer length of the signal transmission line of the SIMM may further compensate for a signal transmission line connected between the first and second sockets which receive the SIMM and DIMM, respectively.

摘要翻译： 一种存储系统系统包括一个单一的在线存储器模块（SIMM），它包含连接在存储器件和连接端子之间的存储器件和信号传输线，以及包含两个存储器的双列直插存储器模块（DIMM） 设备和连接在两个存储设备和连接终端之间的信号传输线。 SIMM的信号传输线的长度长于DIMM的信号传输线的长度。 SIMM的存储器件的负载小于DIMM的存储器件的负载，并且SIMM的信号传输线的较长的长度增加了SIMM的信号延迟时间以补偿SIMM的不同负载 和DIMM存储设备。 SIMM的信号传输线的较长的长度可进一步补偿连接在接收SIMM和DIMM的第一和第二插座之间的信号传输线。