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公开(公告)号：US11923341B2
公开(公告)日：2024-03-05
申请号：US17467011
申请日：2021-09-03
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , G06F3/06 , G06F11/10 , G06F12/0802 , G06N3/02 , H01L25/00 , G11C16/04
CPC分类号： H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US20210398949A1
公开(公告)日：2021-12-23
申请号：US17467011
申请日：2021-09-03
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US12068286B2
公开(公告)日：2024-08-20
申请号：US18138270
申请日：2023-04-24
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , G06F3/06 , G06F11/10 , G06F12/0802 , G06N3/02 , H01L25/00 , G11C16/04
CPC分类号： H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US20230260969A1
公开(公告)日：2023-08-17
申请号：US18138270
申请日：2023-04-24
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802
CPC分类号： H01L25/0657 , H01L25/50 , G06N3/02 , G06F3/0679 , G06F3/0655 , G06F3/0604 , G06F11/1068 , G06F12/0802 , G06F2212/72 , H01L2225/06541 , H01L2225/06513 , G11C16/0483
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US20240363592A1
公开(公告)日：2024-10-31
申请号：US18767750
申请日：2024-07-09
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , G06F3/06 , G06F11/10 , G06F12/0802 , G06N3/02 , G11C16/04 , H01L25/00
CPC分类号： H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory its, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US11670620B2
公开(公告)日：2023-06-06
申请号：US16776279
申请日：2020-01-29
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802 , G11C16/04
CPC分类号： H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US20200243486A1
公开(公告)日：2020-07-30
申请号：US16776279
申请日：2020-01-29
发明人： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC分类号： H01L25/065 , H01L25/00 , G06F3/06 , G06F12/0802 , G06N3/02 , G06F11/10 , G11C16/04
摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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