公开(公告)号：US20210248094A1

公开(公告)日：2021-08-12

申请号：US17169212

申请日：2021-02-05

申请人： SUNRISE MEMORY CORPORATION

发明人： Robert D. Norman ,  Eli Harari ,  Khandker Nazrul Quader ,  Frank Sai-keung Lee ,  Richard S. Chernicoff ,  Youn Cheul Kim ,  Mehrdad Mofidi

IPC分类号： G06F13/16 ,  G06F13/28 ,  G06F9/4401 ,  G06F12/0893 ,  G06F13/42 ,  G06F12/10 ,  G06F9/54 ,  H01L25/065 ,  H01L25/18

摘要： A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

公开(公告)号：US20200243486A1

公开(公告)日：2020-07-30

申请号：US16776279

申请日：2020-01-29

申请人： Sunrise Memory Corporation

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  H01L25/00 ,  G06F3/06 ,  G06F12/0802 ,  G06N3/02 ,  G06F11/10 ,  G11C16/04

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US11923341B2

公开(公告)日：2024-03-05

申请号：US17467011

申请日：2021-09-03

申请人： Sunrise Memory Corporation

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/00 ,  G11C16/04

CPC分类号： H01L25/0657 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/50 ,  G06F2212/60 ,  G06F2212/72 ,  G11C16/0483 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US11580038B2

公开(公告)日：2023-02-14

申请号：US17169212

申请日：2021-02-05

申请人： SUNRISE MEMORY CORPORATION

发明人： Robert D. Norman ,  Eli Harari ,  Khandker Nazrul Quader ,  Frank Sai-keung Lee ,  Richard S. Chernicoff ,  Youn Cheul Kim ,  Mehrdad Mofidi

IPC分类号： G06F13/38 ,  G06F13/16 ,  G06F13/28 ,  G06F9/4401 ,  G06F12/0893 ,  G06F13/42 ,  G06F9/54 ,  H01L25/065 ,  H01L25/18 ,  G06F12/10

摘要： A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

公开(公告)号：US20210398949A1

公开(公告)日：2021-12-23

申请号：US17467011

申请日：2021-09-03

申请人： Sunrise Memory Corporation

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  H01L25/00 ,  G06N3/02 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US20240363592A1

公开(公告)日：2024-10-31

申请号：US18767750

申请日：2024-07-09

申请人： SUNRISE MEMORY CORPORATION

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802 ,  G06N3/02 ,  G11C16/04 ,  H01L25/00

CPC分类号： H01L25/0657 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/50 ,  G06F2212/60 ,  G06F2212/72 ,  G11C16/0483 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory its, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US12105650B2

公开(公告)日：2024-10-01

申请号：US18087661

申请日：2022-12-22

申请人： SUNRISE MEMORY CORPORATION

发明人： Robert D. Norman ,  Eli Harari ,  Khandker Nazrul Quader ,  Frank Sai-keung Lee ,  Richard S. Chernicoff ,  Youn Cheul Kim ,  Mehrdad Mofidi

IPC分类号： G06F12/00 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18

CPC分类号： G06F13/1668 ,  G06F9/4403 ,  G06F9/541 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/28 ,  G06F13/4282 ,  H01L25/0652 ,  H01L25/18 ,  G06F2212/3042 ,  H01L2225/06513 ,  H01L2225/06541

摘要： A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

公开(公告)号：US11670620B2

公开(公告)日：2023-06-06

申请号：US16776279

申请日：2020-01-29

申请人： Sunrise Memory Corporation

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  H01L25/00 ,  G06N3/02 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802 ,  G11C16/04

CPC分类号： H01L25/0657 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/50 ,  G06F2212/60 ,  G06F2212/72 ,  G11C16/0483 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US12068286B2

公开(公告)日：2024-08-20

申请号：US18138270

申请日：2023-04-24

申请人： SUNRISE MEMORY CORPORATION

发明人： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC分类号： H01L25/065 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/00 ,  G11C16/04

CPC分类号： H01L25/0657 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/50 ,  G06F2212/60 ,  G06F2212/72 ,  G11C16/0483 ,  H01L2225/06513 ,  H01L2225/06541

摘要： An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US11823760B2

公开(公告)日：2023-11-21

申请号：US17512449

申请日：2021-10-27

申请人： SUNRISE MEMORY CORPORATION

发明人： Frank Sai-keung Lee

IPC分类号： G11C29/42 ,  G11C29/52 ,  G11C29/18 ,  G11C29/12

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/52

摘要： A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refresh circuit writing back the first portion of the ECC-encoded code word.