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公开(公告)号：US12073082B2
公开(公告)日：2024-08-27
申请号：US18306073
申请日：2023-04-24
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Youn Cheul Kim , Richard S. Chernicoff , Khandker Nazrul Quader , Robert D. Norman , Tianhong Yan , Sayeef Salahuddin , Eli Harari
CPC classification number: G06F3/0611 , G06F3/0631 , H01L24/20 , H01L25/18 , H01L2224/211 , H01L2224/214 , H01L2924/1431 , H01L2924/1435
Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
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公开(公告)号：US20210248094A1
公开(公告)日：2021-08-12
申请号：US17169212
申请日：2021-02-05
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Robert D. Norman , Eli Harari , Khandker Nazrul Quader , Frank Sai-keung Lee , Richard S. Chernicoff , Youn Cheul Kim , Mehrdad Mofidi
IPC: G06F13/16 , G06F13/28 , G06F9/4401 , G06F12/0893 , G06F13/42 , G06F12/10 , G06F9/54 , H01L25/065 , H01L25/18
Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.
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公开(公告)号：US11923341B2
公开(公告)日：2024-03-05
申请号：US17467011
申请日：2021-09-03
Applicant: Sunrise Memory Corporation
Inventor： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC: H01L25/065 , G06F3/06 , G06F11/10 , G06F12/0802 , G06N3/02 , H01L25/00 , G11C16/04
CPC classification number: H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US11580038B2
公开(公告)日：2023-02-14
申请号：US17169212
申请日：2021-02-05
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Robert D. Norman , Eli Harari , Khandker Nazrul Quader , Frank Sai-keung Lee , Richard S. Chernicoff , Youn Cheul Kim , Mehrdad Mofidi
IPC: G06F13/38 , G06F13/16 , G06F13/28 , G06F9/4401 , G06F12/0893 , G06F13/42 , G06F9/54 , H01L25/065 , H01L25/18 , G06F12/10
Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.
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公开(公告)号：US20210398949A1
公开(公告)日：2021-12-23
申请号：US17467011
申请日：2021-09-03
Applicant: Sunrise Memory Corporation
Inventor： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC: H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802
Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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Patent Agency Ranking
公开(公告)号：US20240345736A1
公开(公告)日：2024-10-17
申请号：US18750979
申请日：2024-06-21
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Youn Cheul Kim , Richard S. Chernicoff , Khandker Nazrul Quader , Robert D. Norman , Tianhong Yan , Sayeef Salahuddin , Eli Harari
CPC classification number: G06F3/0611 , G06F3/0631 , H01L24/20 , H01L25/18 , H01L2224/211 , H01L2224/214 , H01L2924/1431 , H01L2924/1435
Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
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公开(公告)号：US20230259283A1
公开(公告)日：2023-08-17
申请号：US18306073
申请日：2023-04-24
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Youn Cheul Kim , Richard S. Chernicoff , Khandker Nazrul Quader , Robert D. Norman , Tianhong Yan , Sayeef Salahuddin , Eli Harari
CPC classification number: G06F3/0611 , H01L24/20 , G06F3/0631 , H01L25/18 , H01L2224/214 , H01L2924/1435 , H01L2924/1431 , H01L2224/211
Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
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公开(公告)号：US20200243486A1
公开(公告)日：2020-07-30
申请号：US16776279
申请日：2020-01-29
Applicant: Sunrise Memory Corporation
Inventor： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC: H01L25/065 , H01L25/00 , G06F3/06 , G06F12/0802 , G06N3/02 , G06F11/10 , G11C16/04
Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US12068286B2
公开(公告)日：2024-08-20
申请号：US18138270
申请日：2023-04-24
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC: H01L25/065 , G06F3/06 , G06F11/10 , G06F12/0802 , G06N3/02 , H01L25/00 , G11C16/04
CPC classification number: H01L25/0657 , G06F3/0604 , G06F3/0655 , G06F3/0679 , G06F11/1068 , G06F12/0802 , G06N3/02 , H01L25/50 , G06F2212/60 , G06F2212/72 , G11C16/0483 , H01L2225/06513 , H01L2225/06541
Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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公开(公告)号：US20230260969A1
公开(公告)日：2023-08-17
申请号：US18138270
申请日：2023-04-24
Applicant: SUNRISE MEMORY CORPORATION
Inventor： Khandker Nazrul Quader , Robert Norman , Frank Sai-keung Lee , Christopher J. Petti , Scott Brad Herner , Siu Lung Chan , Sayeef Salahuddin , Mehrdad Mofidi , Eli Harari
IPC: H01L25/065 , H01L25/00 , G06N3/02 , G06F3/06 , G06F11/10 , G06F12/0802
CPC classification number: H01L25/0657 , H01L25/50 , G06N3/02 , G06F3/0679 , G06F3/0655 , G06F3/0604 , G06F11/1068 , G06F12/0802 , G06F2212/72 , H01L2225/06541 , H01L2225/06513 , G11C16/0483
Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.
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