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    Method of generating modified layout and system therefor
    2.
    发明授权
    Method of generating modified layout and system therefor 有权

    公开(公告)号：US10019548B2

    公开(公告)日：2018-07-10

    申请号：US15651616

    申请日：2017-07-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chia-Ming Ho ,  Ke-Ying Su ,  Hsien-Hsin Sean Lee

    IPC: G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G03F1/70

    CPC classification number: G06F17/5072 ,  G03F1/70 ,  G06F17/5081 ,  G06F2217/12 ,  G21K5/00

    Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.

    Parasitic Capacitance Extraction for FinFETs
    3.
    发明申请
    Parasitic Capacitance Extraction for FinFETs 有权
    FinFET的寄生电容提取

    公开(公告)号：US20140258962A1

    公开(公告)日：2014-09-11

    申请号：US13873969

    申请日：2013-04-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Ze-Ming Wu ,  Hsien-Hsin Sean Lee

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/41791

    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.

    Abstract translation: 一种方法包括生成三维表。 三维表的表格单元包括归一化的寄生电容值，其选自基本上由归一化的多晶对寄生电容值和Fin场效应晶体管（FinFET）的归一化多金属 - 金属 - 接触寄生电容值组成的组 ）。 该三维工作台由FinFET的多金属 - 金属 - 接触间距，FinFET的鳍 - 鳍间距和FinFET的金属 - 接触 - 二 - - - - - - - 间隔来引导。 使用计算机执行生成三维表的步骤。

    Parasitic capacitance extraction for FinFETs
    4.
    发明授权
    Parasitic capacitance extraction for FinFETs 有权
    FinFET的寄生电容提取

    公开(公告)号：US08826213B1

    公开(公告)日：2014-09-02

    申请号：US13873969

    申请日：2013-04-30

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Ze-Ming Wu ,  Hsien-Hsin Sean Lee

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/41791

    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.

    Abstract translation: 一种方法包括生成三维表。 三维表的表格单元包括归一化的寄生电容值，其选自基本上由归一化的多晶对寄生电容值和Fin场效应晶体管（FinFET）的归一化多金属 - 金属 - 接触寄生电容值组成的组 ）。 该三维工作台由FinFET的多金属 - 金属 - 接触间距，FinFET的鳍 - 鳍间距和FinFET的金属 - 接触 - 二 - - - - - - - 间隔来引导。 使用计算机执行生成三维表的步骤。

    Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout
    6.
    发明授权
    Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout 有权
    多重图案化多间隔集成电路布局的电阻电容测定方法

    公开(公告)号：US09218448B2

    公开(公告)日：2015-12-22

    申请号：US14158968

    申请日：2014-01-20

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chia-Ming Ho ,  C. Y. Chen ,  Hsiu-Wen Hsueh ,  Jun-Fu Huang ,  Shao-Heng Chou

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/44 ,  G03F1/70 ,  G03F7/70283 ,  G03F7/70466 ,  G06F17/5009 ,  G06F2217/06 ,  G06F2217/12

    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.

    Abstract translation: 一种方法包括产生与集成电路的布局相关联的多个多个图案化分解。 多个多个图案化分解中的每一个包括与第一掩模相关联的第一图案，与第二掩模相关联的第二图案，第一掩模和第二掩模是多个图案掩模组的两个掩模，与之相关联的宽度值 第一图案或第二图案中的至少一个，以及第一图案和第二图案之间的间隔值。 生成包括与基于宽度值和间隔值的多个多个图案化分解相关联的多个介电常数值的文件。

    Method of generating a simulation model of a predefined fabrication process
    8.
    发明授权
    Method of generating a simulation model of a predefined fabrication process 有权
    生成预定制造过程的仿真模型的方法

    公开(公告)号：US09230052B2

    公开(公告)日：2016-01-05

    申请号：US14531374

    申请日：2014-11-03

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F7/20

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5072

    Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.

    Abstract translation: 根据样品导电特征产生预定制造工艺的仿真模型的方法包括接收导电特征的几何构型和布局设计。 产生基于样品导电特征的几何结构的样品导电特征的电路级仿真模型。 硬件处理器将样本导电特征的电路级仿真模型转换成与布局设计的第一组预定标准相对应的第一布局偏差规则和与第一布局偏置规则不同的第二布局偏置规则， 对应于布局设计的第二组预定标准。

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