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公开(公告)号：US20230371263A1
公开(公告)日：2023-11-16
申请号：US18357240
申请日：2023-07-24
发明人： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
CPC分类号： H10B51/00 , G11C11/223 , H01L29/78391 , H01L29/516 , H01L29/6684 , H01L29/40111
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
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公开(公告)号：US20220139959A1
公开(公告)日：2022-05-05
申请号：US17574010
申请日：2022-01-12
发明人： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
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公开(公告)号：US20220077165A1
公开(公告)日：2022-03-10
申请号：US17528611
申请日：2021-11-17
发明人： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Chih-Hsiang Chang , Fu-Chen Chang
IPC分类号： H01L27/11502 , H01L27/11507 , H01L49/02 , G11C11/22 , H01L27/11504
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.
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公开(公告)号：US09660082B2
公开(公告)日：2017-05-23
申请号：US14102702
申请日：2013-12-11
IPC分类号： H01L29/78 , H01L29/165 , H01L29/66 , H01L21/02 , H01L29/10
CPC分类号： H01L29/785 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/18 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66795 , H01L29/7848
摘要： An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.
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公开(公告)号：US20210035993A1
公开(公告)日：2021-02-04
申请号：US16780418
申请日：2020-02-03
发明人： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
IPC分类号： H01L27/11507 , G11C11/22 , H01L27/11504 , H01L49/02
摘要： In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US10693003B2
公开(公告)日：2020-06-23
申请号：US15600311
申请日：2017-05-19
IPC分类号： H01L29/78 , H01L29/165 , H01L29/66 , H01L29/161 , H01L21/18 , H01L21/02 , H01L29/10
摘要： An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.
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公开(公告)号：US11296099B2
公开(公告)日：2022-04-05
申请号：US16780418
申请日：2020-02-03
发明人： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
IPC分类号： H01L21/00 , H01L27/11507 , H01L27/11504 , G11C11/22 , H01L49/02
摘要： In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US08703565B2
公开(公告)日：2014-04-22
申请号：US13794458
申请日：2013-03-11
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译： 集成电路结构包括在衬底上的衬底和含锗半导体鳍。 含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。
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公开(公告)号：US20130196478A1
公开(公告)日：2013-08-01
申请号：US13794458
申请日：2013-03-11
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译： 集成电路结构包括在衬底上的衬底和含锗半导体鳍。 含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。
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公开(公告)号：US11800720B2
公开(公告)日：2023-10-24
申请号：US17528611
申请日：2021-11-17
发明人： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Chih-Hsiang Chang , Fu-Chen Chang
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.
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