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公开(公告)号：US12058870B2
公开(公告)日：2024-08-06
申请号：US17868278
申请日：2022-07-19
发明人： Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chi On Chui
CPC分类号： H10B51/20 , H01L29/40111 , H01L29/78391 , H01L29/785 , H01L29/78696 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.
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公开(公告)号：US20240251564A1
公开(公告)日：2024-07-25
申请号：US18593959
申请日：2024-03-03
发明人： Sheng-Chen Wang , Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin , Han-Jong Chia
IPC分类号： H10B51/20 , H01L29/417 , H10B51/00 , H10B51/10 , H10B51/30
CPC分类号： H10B51/20 , H01L29/41741 , H01L29/41775 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
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公开(公告)号：US12002534B2
公开(公告)日：2024-06-04
申请号：US17842256
申请日：2022-06-16
发明人： Meng-Han Lin , Chenchen Jacob Wang , Yi-Ching Liu , Han-Jong Chia , Sai-Hooi Yeong , Yu-Ming Lin , Yih Wang
IPC分类号： G11C5/06 , H01L29/24 , H01L29/78 , H01L29/786 , H10B41/27 , H10B51/00 , H10B51/10 , H10B51/20
CPC分类号： G11C5/063 , H01L29/24 , H01L29/78391 , H01L29/7869 , H10B41/27 , H10B51/00 , H10B51/10 , H10B51/20
摘要： Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.
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公开(公告)号：US11862726B2
公开(公告)日：2024-01-02
申请号：US17401315
申请日：2021-08-13
发明人： Hung-Chang Sun , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , Tsuching Yang , Feng-Cheng Yang , Chung-Te Lin
CPC分类号： H01L29/78391 , H01L29/6684 , H10B51/00
摘要： A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.
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公开(公告)号：US11761089B2
公开(公告)日：2023-09-19
申请号：US16827862
申请日：2020-03-24
发明人： Bo-Eun Park , Jooho Lee , Yongsung Kim , Jeonggyu Song
IPC分类号： C23C16/40 , H10B51/00 , C23C16/56 , C23C16/455 , C23C14/58 , C01G27/02 , C23C14/08 , H10B53/00
CPC分类号： C23C16/56 , C01G27/02 , C23C14/08 , C23C14/5806 , C23C16/40 , C23C16/45525 , H10B51/00 , H10B53/00 , C01P2002/72 , C01P2002/76 , C01P2004/24 , C01P2006/40
摘要： A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including HfxA1-xO2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in HfxA1-xO2 is in a range of 0.3 to 0.5.
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6.发明授权公开(公告)号：US11710513B2
公开(公告)日：2023-07-25
申请号：US17696052
申请日：2022-03-16
CPC分类号： G11C11/223 , G11C11/2277 , H10B51/00
摘要： Some embodiments include a ferroelectric transistor having a conductive gate structure, a first ring extending around the conductive gate structure and a second ring extending around the first ring. The first ring includes ferroelectric material. The second ring includes insulative material. A mass of channel material is outward of the second ring. Some embodiments include integrated assemblies and methods of forming integrated assemblies.
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公开(公告)号：US20230157028A1
公开(公告)日：2023-05-18
申请号：US18155688
申请日：2023-01-17
发明人： Sheng-Chen Wang , Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin , Han-Jong Chia
IPC分类号： H10B51/20 , H01L29/417 , H10B51/00 , H10B51/10 , H10B51/30
CPC分类号： H10B51/20 , H01L29/41741 , H01L29/41775 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
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公开(公告)号：US20240274160A1
公开(公告)日：2024-08-15
申请号：US18644516
申请日：2024-04-24
发明人： Meng-Han Lin , Chenchen Jacob Wang , Yi-Ching Liu , Han-Jong Chia , Sai-Hooi Yeong , Yu-Ming Lin , Yih Wang
IPC分类号： G11C5/06 , H01L29/24 , H01L29/78 , H01L29/786 , H10B41/27 , H10B51/00 , H10B51/10 , H10B51/20
CPC分类号： G11C5/063 , H01L29/24 , H01L29/78391 , H01L29/7869 , H10B41/27 , H10B51/00 , H10B51/10 , H10B51/20
摘要： Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.
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公开(公告)号：US11980036B2
公开(公告)日：2024-05-07
申请号：US17873207
申请日：2022-07-26
发明人： Chao-I Wu , Yu-Ming Lin , Han-Jong Chia
CPC分类号： H10B53/00 , G11C5/06 , G11C11/221 , H10B51/00
摘要： A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
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公开(公告)号：US11848193B2
公开(公告)日：2023-12-19
申请号：US18047984
申请日：2022-10-19
申请人： SK hynix Inc.
发明人： Hyangkeun Yoo
CPC分类号： H01L29/78391 , H01L29/0847 , H01L29/516 , H01L29/6684 , H10B51/00
摘要： A ferroelectric semiconductor device includes a substrate having a channel structure, a trench pattern having a bottom surface and a sidewall surface in the channel structure, a dielectric layer disposed on the bottom surface and the sidewall surface of the trench pattern, and a gate electrode layer disposed on the dielectric layer. The dielectric layer includes a ferroelectric layer pattern and a non-ferroelectric layer pattern that are disposed along the sidewall surface of the trench pattern.
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