公开(公告)号：US10998442B2

公开(公告)日：2021-05-04

申请号：US16711497

申请日：2019-12-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/76 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

公开(公告)号：US10468408B2

公开(公告)日：2019-11-05

申请号：US15898785

申请日：2018-02-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chang ,  Jeff J. Xu

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.

公开(公告)号：US09660082B2

公开(公告)日：2017-05-23

申请号：US14102702

申请日：2013-12-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Hao Chang ,  Jeff J. Xu ,  Chien-Hsun Wang ,  Chih Chieh Yeh ,  Chih-Hsiang Chang

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/785 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/18 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7848

摘要： An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

公开(公告)号：US09202915B2

公开(公告)日：2015-12-01

申请号：US13859536

申请日：2013-04-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jeff J. Xu

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L29/045 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/20 ,  H01L29/32 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.

摘要翻译： 本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底中形成沟槽，其中沟槽的底表面具有第一晶面取向，并且沟槽的侧表面具有第二晶体面 取向和外延（epi））在沟槽中生长半导体材料。 epi工艺利用蚀刻部件。 第一晶面取向上的第一生长速率与第二晶面取向上的第二生长速率不同。

公开(公告)号：US09190417B2

公开(公告)日：2015-11-17

申请号：US13757510

申请日：2013-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chang ,  Jeff J. Xu

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L27/12 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成翅片结构，所述翅片结构包括所述半导体衬底上的第一材料部分和所述第一材料部分上的第二材料部分; 在翅片结构的一部分上形成栅极结构，使得栅极结构穿过翅片结构，从而分离翅片结构的源极区域和漏极区域，其中鳍状结构的源极和漏极区域在其间限定通道 ; 从翅片结构的源区和漏区移除第二材料部分; 并且在去除第二材料部分之后，在鳍结构的源极和漏极区域中形成第三材料部分。

公开(公告)号：US09142643B2

公开(公告)日：2015-09-22

申请号：US13677406

申请日：2012-11-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hung Cheng ,  Tsz-Mei Kwok ,  Chun Hsiung Tsai ,  Jeff J. Xu

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides an integrated circuit device and method for manufacturing the integrated circuit device. The disclosed method provides substantially defect free epitaxial features. An exemplary method includes forming a gate structure over the substrate; forming recesses in the substrate such that the gate structure interposes the recesses; and forming source/drain epitaxial features in the recesses. Forming the source/drain epitaxial features includes performing a selective epitaxial growth process to form an epitaxial layer in the recesses, and performing a selective etch back process to remove a dislocation area from the epitaxial layer.

摘要翻译： 本公开提供了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了基本上无缺陷的外延特征。 一种示例性方法包括在衬底上形成栅极结构; 在所述基板中形成凹部，使得所述栅极结构插入所述凹部; 并在凹槽中形成源极/漏极外延特征。 形成源极/漏极外延特征包括执行选择性外延生长工艺以在凹槽中形成外延层，以及执行选择性回蚀工艺以从外延层去除位错区域。

公开(公告)号：US09006056B2

公开(公告)日：2015-04-14

申请号：US13904586

申请日：2013-05-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Liang-Gi Yao ,  Chun-Hu Cheng ,  Chen-Yi Lee ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/8249 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

CPC分类号： H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

摘要： A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700° C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600° C.

摘要翻译： 一种在半导体衬底上的界面层上进行紫外线（UV）固化过程的方法，该方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中 气体包括惰性气体。 该方法还包括在小于或等于700℃的温度下加热界面层。在半导体衬底上的界面层上进行退火处理的另一种方法，第二种方法包括将10sccm的气体流速提供给 5slm，其中气体包括惰性气体。 该方法还包括在小于或等于600℃的温度下加热界面层。

公开(公告)号：US08497177B1

公开(公告)日：2013-07-30

申请号：US13645305

申请日：2012-10-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huicheng Chang ,  Jeff J. Xu ,  Hung-Ta Lin ,  Chun-Feng Nieh

IPC分类号： H01L21/336

CPC分类号： H01L29/66795

摘要： A method for fabricating a fin field-effect transistor (FinFET) device includes providing a substrate having a first fin at a first location, and epitaxially growing a second fin on the substrate at the first location. The epitaxial growth is performed at a first temperature. The method further includes performing a thermal annealing at a second temperature in oxygen ambient on the substrate with the second fin thereon to grow an interface wrapping over the second fin. The second temperature is higher than the first temperature.

摘要翻译： 一种制造鳍状场效应晶体管（FinFET）器件的方法包括：在第一位置提供具有第一鳍片的衬底，以及在第一位置在衬底上外延生长第二鳍片。 在第一温度下进行外延生长。 该方法还包括在氧气环境中的第二温度下在其上具有第二散热片的基板上进行热退火，以使覆盖在第二散热片上的界面成长。 第二温度高于第一温度。

公开(公告)号：US11251303B2

公开(公告)日：2022-02-15

申请号：US16986043

申请日：2020-08-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/76 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

公开(公告)号：US10693003B2

公开(公告)日：2020-06-23

申请号：US15600311

申请日：2017-05-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chang ,  Jeff J. Xu ,  Chien-Hsun Wang ,  Chih Chieh Yeh ,  Chih-Hsiang Chang

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161 ,  H01L21/18 ,  H01L21/02 ,  H01L29/10

摘要： An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.