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公开(公告)号：US20240223087A1
公开(公告)日：2024-07-04
申请号：US18608197
申请日：2024-03-18
发明人： Chu Fu CHEN , Chi-Feng HUANG , Chia-Chung CHEN , Chin-Lung CHEN , Victor Chiang LIANG , Chia-Cheng PAO
IPC分类号： H02M3/158 , H01L21/84 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/80 , H01L21/265
CPC分类号： H02M3/1582 , H01L21/84 , H01L29/0847 , H01L29/4232 , H01L29/66659 , H01L29/7835 , H01L29/7836 , H01L29/80 , H01L21/26586 , H02M3/158
摘要： A method of making a semiconductor device includes implanting a source/drain (S/D) in the substrate adjacent to a gate structure. The method further includes implanting a lightly doped drain (LDD) region in the substrate in direct contact with the S/D, wherein a dopant concentration in the LDD region is less than a dopant concentration in the S/D. The method further includes implanting a doping extension region in the substrate in direct contact with the LDD region, wherein a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
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公开(公告)号：US20210028309A1
公开(公告)日：2021-01-28
申请号：US17027032
申请日：2020-09-21
发明人： Chu Fu CHEN , Chi-Feng HUANG , Chia-Chung CHEN , Chin-Lung CHEN , Victor Chiang LIANG , Chia-Cheng PAO
摘要： A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
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3.发明申请公开(公告)号：US20150212146A1
公开(公告)日：2015-07-30
申请号：US14163062
申请日：2014-01-24
发明人： Chun Hao LIAO , Chu Fu CHEN , Po-Ju CHIU , Jun Yean CHIOU , Chao-Jen CHENG
CPC分类号： G01R31/2648 , G01R31/2831 , H01L22/12 , H01L22/34
摘要： A semiconductor device comprises a first layer, a second layer configured to overlap with the first layer at a plurality of positions, a plurality of first layer contacts configured to be selectively activated to test the first layer for a first layer leakage current, and a plurality of second layer contacts configured to be selectively activated to test the second layer for a second layer leakage current. The first layer contacts are arranged on the first layer on a first side and a second side of the plurality of positions at which the second layer overlaps with the first layer. The second layer contacts are arranged on the second layer on a third side and a fourth side of the plurality of positions at which the second layer overlaps with the first layer. A determined first layer leakage current or second layer leakage current is indicative of the presence of a crystal defect in the semiconductor device.
摘要翻译： 半导体器件包括第一层，被配置为在多个位置处与第一层重叠的第二层，被配置为选择性地激活以测试第一层以获得第一层漏电流的多个第一层触点，以及多个 的第二层接触，被配置为选择性地激活以测试第二层以获得第二层泄漏电流。 第一层接触件布置在第二层与第一层重叠的多个位置的第一侧和第二侧上的第一层上。 在第二层与第一层重叠的多个位置的第三侧和第四侧上，在第二层上布置第二层接触。 确定的第一层漏电流或第二层漏电流表示半导体器件中存在晶体缺陷。
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公开(公告)号：US20200152526A1
公开(公告)日：2020-05-14
申请号：US16739941
申请日：2020-01-10
发明人： Chun Hao LIAO , Chu Fu CHEN , Mingo LIU , Chiou Jun YEAN
IPC分类号： H01L21/66 , H01L25/16 , H01L25/075
摘要： An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.
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5.发明申请公开(公告)号：US20190165678A1
公开(公告)日：2019-05-30
申请号：US15938482
申请日：2018-03-28
发明人： Chu Fu CHEN , Chi-Feng HUANG , Chia-Chung CHEN , Chin-Lung CHEN , Victor Chiang LIANG , Chia-Cheng PAO
IPC分类号： H02M3/158 , H01L29/423 , H01L29/08 , H01L29/80 , H01L21/84
摘要： A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
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公开(公告)号：US20170301659A1
公开(公告)日：2017-10-19
申请号：US15193542
申请日：2016-06-27
发明人： Chun Hao LIAO , Chu Fu CHEN , Mingo LIU , Chiou Jun YEAN
CPC分类号： H01L22/14 , G01R31/2635 , H01L22/34 , H01L25/0753 , H01L25/165 , H01L33/0079 , H01L33/0095 , H01L2933/0033
摘要： An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.
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