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    MEMORY AND METHOD OF OPERATING THE SAME
    6.
    发明申请
    MEMORY AND METHOD OF OPERATING THE SAME 审中-公开
    存储器及其操作方法

    公开(公告)号：US20160019939A1

    公开(公告)日：2016-01-21

    申请号：US14870402

    申请日：2015-09-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jung-Ping YANG ,  Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Chia-En HUANG ,  Cheng Hung LEE

    IPC分类号： G11C7/12 ,  G11C7/10

    CPC分类号： G11C7/12 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/18 ,  G11C11/419 ,  G11C2207/005

    摘要： A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.

    摘要翻译： 存储器包括多个存储器块，多个感测电路，多个全局位线，公共预充电电路和选择电路。 多个全局位线的每个全局位线通过多个检测电路的对应检测电路耦合到至少一个存储器块。 公共预充电电路被配置为单独地将多个全局位线中的每个全局位线预充电为预充电电压。 选择电路被配置为选择性地将公共预充电电路耦合到多个全局位线的选定的全局位线。

    DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT
    7.
    发明申请
    DEVICE HAVING MULTIPLE-LAYER PINS IN MEMORY MUX1 LAYOUT 有权
    在存储器MUX1布局中具有多个引脚的器件

    公开(公告)号：US20150162273A1

    公开(公告)日：2015-06-11

    申请号：US14102623

    申请日：2013-12-11

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hung-Jen LIAO ,  Jung-Hsuan CHEN ,  Chien Chi TIEN ,  Ching-Wei WU ,  Jui-Che TSAI ,  Hong-Chen CHENG ,  Chung-Hsing WANG

    IPC分类号： H01L23/498 ,  H01L27/11

    CPC分类号： H01L23/50 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L27/0203 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.

    摘要翻译： 一种集成电路（IC）存储器件，其包括第一导电层，电耦合到第一导电层的第二导电层，形成在第一导电层上的第二导电层，与第二导电层分离的第三导电层， 形成在所述第二导电层上的第三导电层，电耦合到所述第三导电层的第四导电层，形成在所述第三导电层上的所述第四导电层，形成在所述第一导电层中或与所述第二导电层电连接的第二导电层， 导电层和形成在第三导电层或第四导电层中并电耦合到第三导电层的1P1E引脚盒。

    SENSE AMPLIFIER
    8.
    发明申请
    SENSE AMPLIFIER 有权
    感应放大器

    公开(公告)号：US20140269128A1

    公开(公告)日：2014-09-18

    申请号：US14214325

    申请日：2014-03-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Kai HSIEH ,  Hong-Chen CHENG ,  Cheng Hung LEE

    IPC分类号： G11C7/06 ,  G11C7/08

    CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C7/1048

    摘要： A sense amplifier includes a cross latch, a first pass gate, a second pass gate, a first data line, a second data line, a first circuit, and a second circuit. The cross latch has a first input/output (I/O) node and a second I/O node. The first pass gate is coupled between the first data line and the first I/O node. The second pass gate is coupled between the second data line and the second I/O node. The first circuit is coupled with the first I/O node and the second data line. The second circuit is coupled with the second I/O node and the first data line. The first circuit is configured to be turned off when the second data line has a first logical value and to be at least lightly turned on when the second data line has a voltage level between the first logical value and a second logical value different from the first logical value. The second circuit is configured to be turned off when the first data line has the first logical value and to be at least lightly turned on when the first data line has a voltage level between the first logical value and the second logical value.

    摘要翻译： 读出放大器包括交叉锁存器，第一通道门，第二通道门，第一数据线，第二数据线，第一电路和第二电路。 交叉锁存器具有第一输入/输出（I / O）节点和第二I / O节点。 第一传输门耦合在第一数据线和第一I / O节点之间。 第二传输门耦合在第二数据线和第二I / O节点之间。 第一电路与第一I / O节点和第二数据线相连。 第二电路与第二I / O节点和第一数据线相连。 当第二数据线具有第一逻辑值和与第一逻辑值不同的第二逻辑值之间的电压电平时，第一电路被配置为在第二数据线具有第一逻辑值时被截止并且至少轻微导通， 逻辑值。 第二电路被配置为当第一数据线具有第一逻辑值时被关断并且当第一数据线具有第一逻辑值和第二逻辑值之间的电压电平时至少轻微导通。

    MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE
    9.
    发明申请
    MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE 有权
    改进设计规范，以提高设备性能

    公开(公告)号：US20130311964A1

    公开(公告)日：2013-11-21

    申请号：US13949683

    申请日：2013-07-24

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

    摘要： A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

    摘要翻译： 设计器件布局的方法包括设计多个器件的栅极结构和扩散区域的布局。 该方法还包括识别多个设备中的边缘设备。 该方法还包括在边缘装置旁边添加一个虚拟装置和在该虚拟装置旁边的一个虚拟栅极结构，其中该虚拟装置与该边缘装置共享扩散区，并且其中该伪装置的栅极结构被认为是 在边缘设备旁边添加了两个虚拟门结构之一。

    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190325104A1

    公开(公告)日：2019-10-24

    申请号：US16458418

    申请日：2019-07-01

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

    IPC分类号： G06F17/50 ,  H01L27/088

    摘要： A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.