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    FinFET with rounded source/drain profile
    4.
    发明授权
    FinFET with rounded source/drain profile 有权

    公开(公告)号：US10861975B2

    公开(公告)日：2020-12-08

    申请号：US16544490

    申请日：2019-08-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ming-Hua Yu ,  Chih-Pin Tsao ,  Pei-Ren Jeng ,  Tze-Liang Lee

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417

    摘要： A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.

    Semiconductor device and method
    5.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US10515858B1

    公开(公告)日：2019-12-24

    申请号：US16584295

    申请日：2019-09-26

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Jing Lee ,  Tsung-Hsi Yang ,  Ming-Hua Yu

    IPC分类号： H01L21/8238 ,  H01L27/092

    摘要： An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

    FinFET with Rounded Source/Drain Profile
    7.
    发明申请
    FinFET with Rounded Source/Drain Profile 有权
    FinFET具有圆形源/排水廓线

    公开(公告)号：US20140252489A1

    公开(公告)日：2014-09-11

    申请号：US13792475

    申请日：2013-03-11

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ming-Hua Yu ,  Chih-Pin Tsao ,  Pei-Ren Jeng ,  Tze-Liang Lee

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/785 ,  H01L29/66477 ,  H01L29/66795

    摘要： A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.

    摘要翻译： 形成具有圆形源极/漏极分布的FinFET的方法包括在衬底中形成翅片，蚀刻鳍片中的源极/漏极凹槽，在源极/漏极凹槽中形成多个源极/漏极层; 以及蚀刻所述多个源极/漏极层中的至少一个。 源极/漏极层可以是硅锗化合物。 源极/漏极层处的蚀刻可以在形成多个源极/漏极层的后续层之前部分地蚀刻多个源极/漏极层中的每一个。 源极/漏极层可以形成在约15nm的顶角处的厚度，并且在形成多个源极/漏极层的后续层之前，源极/漏极层可以各自被蚀刻回约3nm。 形成多个源极/漏极层可选地包括形成至少五个源极/漏极层。

    EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION
    8.
    发明公开
    EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION 审中-公开

    公开(公告)号：US20230387204A1

    公开(公告)日：2023-11-30

    申请号：US17824915

    申请日：2022-05-26

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chih Sheng Huang ,  Ming-Hua Yu ,  Yee-Chia Yeo

    IPC分类号： H01L29/08 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/0847 ,  H01L29/045 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/66795 ,  H01L21/02532

    摘要： A semiconductor device includes a plurality of nanostructures, a gate dielectric layer disposed on each nanostructure of the plurality of nanostructures, a gate electrode disposed on the gate dielectric layer and on the plurality of nanostructures, and a source/drain region adjacent to the nanostructures. The source/drain region includes an epitaxial structure including a polygonal-shaped upper portion and a column-like lower portion, wherein the polygonal-shaped upper portion has multiple facets, and each of the facets characterized by a (111) crystallographic orientation. The polygonal-shaped upper portion includes corner regions adjacent an intersection of two facets with a (111) crystallographic orientation and an epitaxial body region in contact with the corner regions. The corner regions are characterized by a first dopant concentration and the epitaxial body region is characterized by a second dopant concentration, and the first dopant concentration is higher than the second dopant concentration.

    Transistors with stacked semiconductor layers as channels
    10.
    发明授权
    Transistors with stacked semiconductor layers as channels 有权

    公开(公告)号：US11257908B2

    公开(公告)日：2022-02-22

    申请号：US16542523

    申请日：2019-08-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Hsi Yang ,  Ming-Hua Yu ,  Jeng-Wei Yu

    IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/167

    摘要： A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.