公开(公告)号：US20220262725A1

公开(公告)日：2022-08-18

申请号：US17732556

申请日：2022-04-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Tze-Liang Lee

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

摘要： An interconnect structure includes an interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

公开(公告)号：US20220216147A1

公开(公告)日：2022-07-07

申请号：US17701702

申请日：2022-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Yu Chou ,  Jr-Hung Li ,  Liang-Yin Chen ,  Su-Hao Liu ,  Tze-Liang Lee ,  Meng-Han Chou ,  Kuo-Ju Chen ,  Huicheng Chang ,  Tsai-Jung Ho ,  Tzu-Yang Ho

IPC分类号： H01L23/522 ,  H01L29/08 ,  H01L23/532 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/02

摘要： A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

公开(公告)号：US11257951B2

公开(公告)日：2022-02-22

申请号：US17089229

申请日：2020-11-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Lilly Su ,  Chii-Horng Li ,  Ming-Hua Yu ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Yen-Ru Lee

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L27/06 ,  H01L29/06

摘要： A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.

公开(公告)号：US11107921B2

公开(公告)日：2021-08-31

申请号：US16696753

申请日：2019-11-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Eric Peng ,  Chao-Cheng Chen ,  Chii-Horng Li ,  Ming-Hua Yu ,  Shih-Hao Lo ,  Syun-Ming Jang ,  Tze-Liang Lee ,  Ying Hao Hsieh

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66

摘要： A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

公开(公告)号：US11049763B2

公开(公告)日：2021-06-29

申请号：US16694406

申请日：2019-11-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Kai Chen ,  Jung-Hau Shiu ,  Chia Cheng Chou ,  Chung-Chi Ko ,  Tze-Liang Lee ,  Chih-Hao Chen ,  Shing-Chyang Pan

IPC分类号： H01L21/768 ,  H01L21/311

摘要： A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

公开(公告)号：US10727342B2

公开(公告)日：2020-07-28

申请号：US16139752

申请日：2018-09-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

公开(公告)号：US10727045B2

公开(公告)日：2020-07-28

申请号：US15967480

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wan-Lin Tsai ,  Jung-Hau Shiu ,  Ching-Yu Chang ,  Jen Hung Wang ,  Shing-Chyang Pan ,  Tze-Liang Lee

IPC分类号： H01L21/768 ,  C23C16/02 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  C23C16/04 ,  C23C16/30 ,  C23C16/455 ,  C23C16/40 ,  C23C14/08 ,  C23C14/06 ,  H01L21/308 ,  H01L29/66 ,  H01J37/32 ,  C23C14/22

摘要： A method of manufacturing a semiconductor device includes depositing a dielectric layer over a substrate, performing a first patterning to form an opening in the dielectric layer, and depositing an oxide film over and contacting the dielectric layer and within the opening in the dielectric layer. The oxide film is formed from multiple precursors that are free of O2, and depositing the oxide film includes forming a plasma of a first precursor of the multiple precursors.

公开(公告)号：US10388792B2

公开(公告)日：2019-08-20

申请号：US15822937

申请日：2017-11-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hua Yu ,  Chih-Pin Tsao ,  Pei-Ren Jeng ,  Tze-Liang Lee

IPC分类号： H01L29/78 ,  H01L29/66

摘要： A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.

公开(公告)号：US10312075B2

公开(公告)日：2019-06-04

申请号：US14989227

申请日：2016-01-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wan-Yi Kao ,  Kuang-Yuan Hsu ,  Tze-Liang Lee

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311

摘要： A method of descumming a dielectric layer is provided. In an embodiment the dielectric layer is deposited over a substrate, and a photoresist is applied, exposed, and developed after the photoresist has been applied. Once the pattern of the photoresist is transferred to the underlying dielectric layer, a descumming process is performed, wherein the descumming process utilizes a mixture of a carbon-containing precursor, a descumming precursor, and a carrier gas. The mixture is ignited into a treatment plasma, and the treatment plasma is applied to the dielectric layer in order to descum the dielectric layer.

公开(公告)号：US20190115470A1

公开(公告)日：2019-04-18

申请号：US16213049

申请日：2018-12-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.