公开(公告)号：US20210328047A1

公开(公告)日：2021-10-21

申请号：US17364623

申请日：2021-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092

摘要： In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

公开(公告)号：US20190341472A1

公开(公告)日：2019-11-07

申请号：US15967672

申请日：2018-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/36

摘要： A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US20190341471A1

公开(公告)日：2019-11-07

申请号：US16511580

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

公开(公告)号：US10170375B2

公开(公告)日：2019-01-01

申请号：US15404937

申请日：2017-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/10

摘要： A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

公开(公告)号：US20170352596A1

公开(公告)日：2017-12-07

申请号：US15687753

申请日：2017-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/165 ,  H01L29/161 ,  H01L29/15 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/321 ,  H01L29/78 ,  H01L29/43

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US20170309730A1

公开(公告)日：2017-10-26

申请号：US15647820

申请日：2017-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

公开(公告)号：US09748142B2

公开(公告)日：2017-08-29

申请号：US15173974

申请日：2016-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Chi-Wen Liu

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L29/15 ,  H01L29/161 ,  H01L29/43

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7849 ,  H01L29/785

摘要： A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

公开(公告)号：US09722051B2

公开(公告)日：2017-08-01

申请号：US14845733

申请日：2015-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3065

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

公开(公告)号：US20170179291A1

公开(公告)日：2017-06-22

申请号：US15450201

申请日：2017-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Chi-Wen Liu ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/778 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L29/161 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66712 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7802 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US09450098B2

公开(公告)日：2016-09-20

申请号：US14625803

申请日：2015-02-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/267 ,  H01L29/165 ,  H01L21/02 ,  H01L29/04 ,  H01L29/15 ,  H01L29/161 ,  H01L29/205 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/7851 ,  H01L21/02532 ,  H01L21/02538 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) device is provided. The FinFET includes a superlattice layer and a strained layer. The superlattice layer is supported by a substrate. The strained layer is disposed on the superlattice layer and provides a gate channel. The gate channel is stressed by the superlattice layer. In an embodiment, the superlattice layer is formed by stacking different silicon germanium alloys or stacking other III-V semiconductor materials.