公开(公告)号：USRE46336E1

公开(公告)日：2017-03-07

申请号：US14120258

申请日：2014-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

IPC: H03D13/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Abstract translation: 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

公开(公告)号：US08804450B2

公开(公告)日：2014-08-12

申请号：US13790726

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Steven Swei ,  David B. Scott

IPC: G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/413

Abstract: A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.

Abstract translation: 一种存储器电路，包括至少一个存储器阵列和连接到所述至少一个存储器阵列并连接到第一电源线以提供第一电源电压的至少一个睡眠晶体管。 存储器电路还包括直接连接到至少一个存储器阵列并且直接连接到第一电源线的至少一个二极管连接的晶体管，以及与所述至少一个二极管连接的晶体管的大部分电耦合的背偏置电路。

公开(公告)号：US09442506B2

公开(公告)日：2016-09-13

申请号：US14051631

申请日：2013-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Chieh Huang ,  Tien-Chun Yang ,  Steven Swei

IPC: G05F3/30 ,  H03K3/2893 ,  G05F3/02 ,  G05F3/24

CPC classification number: G05F3/02 ,  G05F3/245

Abstract: A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output.

Abstract translation: 具有温度补偿的电压参考电路包括电源，第一参考电压源，第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，连接到第二NMOS源极和地的电阻。 电压参考电路还包括第二参考电压源，第三PMOS晶体管，第四PMOS晶体管，第三NMOS晶体管，第四NMOS晶体管和第五NMOS晶体管，漏极连接到第四NMOS晶体管的源极， 连接到地的源极和连接到第一参考电压输出的栅极。

公开(公告)号：USRE46107E1

公开(公告)日：2016-08-16

申请号：US14284181

申请日：2014-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G05F1/10 ,  G05F3/02 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract translation: 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。

公开(公告)号：US09086330B2

公开(公告)日：2015-07-21

申请号：US13915236

申请日：2013-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chan-Hong Chern ,  Steven Swei

IPC: G01K7/14 ,  G01K7/01

CPC classification number: G01K7/14 ,  G01K7/01 ,  G01K2219/00

Abstract: A circuit includes a comparator, a first circuit, and a second circuit. The comparator has a first input node and a second input node. The first circuit is configured to output a temperature-dependent voltage at the first input node of the comparator. The first circuit includes a current mirror configured to generate a first reference voltage. The second circuit is configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

Abstract translation: 电路包括比较器，第一电路和第二电路。 比较器具有第一输入节点和第二输入节点。 第一电路被配置为在比较器的第一输入节点处输出与温度有关的电压。 第一电路包括被配置为产生第一参考电压的电流镜。 第二电路被配置为响应于数字码和第一参考电压在比较器的第二输入节点处输出第二参考电压。