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    Level shifting circuit, apparatus and method of operating the same
    4.
    发明授权
    Level shifting circuit, apparatus and method of operating the same 有权

    公开(公告)号：US09871521B2

    公开(公告)日：2018-01-16

    申请号：US15049919

    申请日：2016-02-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tsung-Ching (Jim) Huang ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin

    IPC: H03K19/0185

    CPC classification number: H03K19/018507 ,  H03K19/0185 ,  H03K19/018521

    Abstract: A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage. The input circuit is configured to receive a first voltage and a second voltage. The leakage divider circuit is configured to receive a third voltage. The leakage divider circuit is connected to the input circuit. The skew inverter circuit is configured to receive the third voltage. The skew inverter circuit is connected to the leakage divider circuit and the input circuit. The buffering circuit has a terminal configured to output an output voltage. The buffering circuit is connected to an output terminal of the skew inverter circuit. The level shifting circuit is free of capacitors.

    Clock generation circuit
    5.
    发明授权
    Clock generation circuit 有权

    公开(公告)号：US09831860B2

    公开(公告)日：2017-11-28

    申请号：US15003330

    申请日：2016-01-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC: H03K3/00 ,  H03K5/151

    CPC classification number: H03K5/1515

    Abstract: A clock generation circuit includes a two-phase non-overlapping clock generation circuit, an inverter, and a delay circuit. The two-phase non-overlapping clock generation circuit is configured to generate a first phase clock signal and a second phase clock signal based on a non-inverted clock signal and an inverted clock signal. The first phase clock signal and the second phase clock signal correspond to a same logical value during a first duration and a second duration within a clock cycle. The inverter is configured to generate the inverted clock signal based on an input clock signal. The delay circuit is configured to generate the non-inverted clock signal based on the input clock signal. The delay circuit has a predetermined delay sufficient to cause a difference between the first duration and the second duration to be less than a predetermined tolerance.

    Input/output circuit and method
    9.
    发明授权
    Input/output circuit and method 有权

    公开(公告)号：US11128285B2

    公开(公告)日：2021-09-21

    申请号：US16883375

    申请日：2020-05-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chan-Hong Chern ,  Tsung-Ching Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Fu-Lung Hsueh

    IPC: H03K5/131 ,  H03K5/1534 ,  H03K17/16 ,  H03K19/003 ,  H03K17/687 ,  H03K5/00

    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.

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