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    Clock generation circuit and charge pumping system
    1.
    发明授权
    Clock generation circuit and charge pumping system 有权

    公开(公告)号：US10778203B2

    公开(公告)日：2020-09-15

    申请号：US16687315

    申请日：2019-11-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC: H03K3/00 ,  H03K5/151

    Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

    Clock generation circuit and charge pumping system
    5.
    发明授权
    Clock generation circuit and charge pumping system 有权

    公开(公告)号：US10355682B2

    公开(公告)日：2019-07-16

    申请号：US15823242

    申请日：2017-11-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tien-Chun Yang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC: G06F1/04 ,  H03L3/00 ,  H03K5/151

    Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.

    Charge pump circuit and method of operating same
    6.
    发明授权
    Charge pump circuit and method of operating same 有权

    公开(公告)号：US10277118B2

    公开(公告)日：2019-04-30

    申请号：US15719755

    申请日：2017-09-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Qing Dong ,  Tien-Chun Yang ,  Yue-Der Chih

    IPC: G05F1/10 ,  H02M3/07

    Abstract: In a charge pump circuit, a first circuit is configured to provide a first node with a first first-voltage level or a first second-voltage level. A second circuit is configured to provide a second node with a second first-voltage level or a second second-voltage level. The first node is coupled with a first end of a first capacitive element. The second node is coupled with a first end of a second capacitive element. A first end of a first voltage transfer circuit is configured to receive an input voltage. A second end of the first voltage transfer circuit is coupled with a second end of the first capacitive element and a first end of a second voltage transfer circuit. A second end of the second voltage transfer circuit is coupled with a second end of the second capacitive element, and is configured to provide an output voltage.

    Phase-lock assistant circuitry
    7.
    再颁专利
    Phase-lock assistant circuitry 有权
    锁相辅助电路

    公开(公告)号：USRE46336E1

    公开(公告)日：2017-03-07

    申请号：US14120258

    申请日：2014-05-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chih-Chang Lin ,  Chan-Hong Chern ,  Steven Swei ,  Ming-Chieh Huang ,  Tien-Chun Yang

    IPC: H03D13/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087

    CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

    Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

    Abstract translation: 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

    Delay line circuit
    8.
    发明授权
    Delay line circuit 有权
    延迟线电路

    公开(公告)号：US09584107B2

    公开(公告)日：2017-02-28

    申请号：US14555198

    申请日：2014-11-26

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Tien-Chun Yang

    IPC: H03H11/26 ,  H03K5/134 ,  H03K5/14 ,  H03K5/00

    CPC classification number: H03K5/134 ,  H03K5/14 ,  H03K2005/00019 ,  H03K2005/00052 ,  H03K2005/00195

    Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.

    Abstract translation: 延迟线电路包括被配置为接收输入信号并提供第一输出信号的多个延迟单元。 多个延迟单元被配置为基于从延迟线控制器​​接收的第一指令来选择性地反转或中继输入信号以产生第一输出信号。 相位插值器单元包括偏移单元，该偏移单元被配置为基于从延迟线控制器​​接收的第二指令来选择性地在相位插值器单元中添加速度控制单元。 相位插值器单元还被配置为接收第一输出信号并提供第二输出信号。

    Dynamic reference current sensing
    9.
    发明授权
    Dynamic reference current sensing 有权

    公开(公告)号：US11094384B2

    公开(公告)日：2021-08-17

    申请号：US16774938

    申请日：2020-01-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Tien-Chun Yang

    IPC: G11C16/28 ,  H03K5/24 ,  G11C7/06 ,  G11C11/16 ,  G11C7/00 ,  G11C7/14 ,  G11C11/56 ,  G11C16/34 ,  G11C29/02 ,  G11C16/30 ,  G11C5/02

    Abstract: A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.

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