公开(公告)号：US20150295088A1

公开(公告)日：2015-10-15

申请号：US14752480

申请日：2015-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Che Tsai ,  Yi-Feng Chang ,  Jam-Wem Lee

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785

摘要： An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

摘要翻译： 实施例集成电路（例如，二极管）及其制造方法。 实施例集成电路包括具有形成在具有第一掺杂类型的衬底上的第一掺杂类型的阱，所述阱包括鳍状物，源极在鳍的第一侧上形成在阱上，源具有第二掺杂型， 在鳍的第二侧上的阱上形成的漏极，具有第一掺杂类型的漏极和形成在鳍上的栅极氧化物，栅极氧化物通过鳍片的退避区域与源极横向间隔开。 该集成电路与FinFET制造工艺兼容。

公开(公告)号：US20170117390A1

公开(公告)日：2017-04-27

申请号：US15398576

申请日：2017-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jam-Wem Lee ,  Tsung-Che Tsai ,  Yi-Feng Chang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/785 ,  H01L29/7853

摘要： A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.

公开(公告)号：US09209302B2

公开(公告)日：2015-12-08

申请号：US14090763

申请日：2013-11-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Che Tsai ,  Yi-Feng Chang ,  Jam-Wem Lee

IPC分类号： H01L21/3205 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/785 ,  H01L29/7853

摘要： A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.

摘要翻译： 形成集成电路器件的方法包括：形成覆盖半导体鳍片的中间部分的栅极叠层，在栅极叠层和半导体鳍片上形成栅极间隔层，并构图栅极间隔层。 所得到的间隔物包括在栅叠层的侧壁上的栅极间隔物，以及在半导体鳍的端部的侧壁上的翅片间隔物。 然后对鳍片间隔物进行蚀刻。 当蚀刻完成时，翅片间隔件的高度小于半导体鳍片的高度的大约一半。

公开(公告)号：US08906767B2

公开(公告)日：2014-12-09

申请号：US14106100

申请日：2013-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/36

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US09887275B2

公开(公告)日：2018-02-06

申请号：US15398576

申请日：2017-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jam-Wem Lee ,  Tsung-Che Tsai ,  Yi-Feng Chang

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/785 ,  H01L29/7853

摘要： A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.

公开(公告)号：US20160093705A1

公开(公告)日：2016-03-31

申请号：US14961048

申请日：2015-12-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jam-Wem Lee ,  Tsung-Che Tsai ,  Yi-Feng Chang

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4975 ,  H01L29/785 ,  H01L29/7853

摘要： A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.

摘要翻译： 形成集成电路器件的方法包括：形成覆盖半导体鳍片的中间部分的栅极叠层，在栅极叠层和半导体鳍片上形成栅极间隔层，并构图栅极间隔层。 所得到的间隔物包括位于栅极叠层的侧壁上的栅极间隔物，以及在半导体鳍片的端部的侧壁上的翅片间隔物。 然后对鳍片间隔物进行蚀刻。 当蚀刻完成时，翅片间隔件的高度小于半导体鳍片的高度的大约一半。

公开(公告)号：US09236733B2

公开(公告)日：2016-01-12

申请号：US13952417

申请日：2013-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Ti Su ,  Wun-Jie Lin ,  Tsung-Che Tsai ,  Jen-Chou Tseng

IPC分类号： H02H9/04 ,  H01L29/74 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0262 ,  H01L29/7436

摘要： A semiconductor device is disclosed that includes a first well of a first conductivity type, a second well of a second conductivity type, a plurality of first regions, a second region and a plurality of electrodes. The first regions are of the first conductivity type and are formed in the second well. The second region is of the second conductivity type and is formed in the first well. Each of the electrodes is formed upon the second well and between adjacent two first regions of the first regions.

摘要翻译： 公开了一种半导体器件，其包括第一导电类型的第一阱，第二导电类型的第二阱，多个第一区域，第二区域和多个电极。 第一区域是第一导电类型并且形成在第二阱中。 第二区域是第二导电类型并形成在第一阱中。 每个电极形成在第二阱上并且在第一区域的相邻两个第一区域之间。

公开(公告)号：US09601627B2

公开(公告)日：2017-03-21

申请号：US15181232

申请日：2016-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Che Tsai ,  Yi-Feng Chang ,  Jam-Wem Lee

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7851 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785

摘要： An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

公开(公告)号：US20160284849A1

公开(公告)日：2016-09-29

申请号：US15181232

申请日：2016-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Che Tsai ,  Yi-Feng Chang ,  Jam-Wem Lee

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785

摘要： An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

公开(公告)号：US20150137174A1

公开(公告)日：2015-05-21

申请号：US14593894

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

IPC分类号： H01L27/02 ,  H01L29/812 ,  H01L21/8248

CPC分类号： H01L27/0262 ,  H01L21/8248 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0921 ,  H01L29/0619 ,  H01L29/73 ,  H01L29/812

摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

摘要翻译： 提高保持电压SCR的方法和装置。 半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。 公开了用于形成装置的方法。