公开(公告)号：US10096589B2

公开(公告)日：2018-10-09

申请号：US14796834

申请日：2015-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Bo-Ting Chen ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/02 ,  H01L27/24 ,  H01L29/66 ,  H01L29/861 ,  H01L27/06

摘要： A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area.

公开(公告)号：US09318621B2

公开(公告)日：2016-04-19

申请号：US13789909

申请日：2013-03-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sun-Jay Chang ,  Ming-Hsiang Song ,  Jen-Chou Tseng ,  Wun-Jie Lin ,  Bo-Ting Chen

IPC分类号： H01L29/861 ,  H01L29/66 ,  H01L27/02 ,  H01L29/06

CPC分类号： H01L29/0692 ,  H01L21/2253 ,  H01L27/0255 ,  H01L29/6609 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/861 ,  H01L29/868

摘要： A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.

摘要翻译： 二极管包括具有平行于第一方向的纵向方向的第一组多个组合翅片，其中所述第一组合翼片包括第一导电类型的部分。 二极管还包括具有与第一方向平行的长度方向的第二组合翅片，其中第二组合翅片包括与第一导电类型相反的第二导电类型的部分。 隔离区域位于第一组合翅片和第二组合翅片之间。 第一和第二多个组合翅片形成二极管的阴极和阳极。 二极管被配置为具有在垂直于第一方向的第二方向上流动的电流，其中电流在阳极和阴极之间流动。

公开(公告)号：US20150062761A1

公开(公告)日：2015-03-05

申请号：US14031826

申请日：2013-09-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hui Chen ,  Chia-Hung Chu ,  Kuo-Ji Chen ,  Ming-Hsiang Song ,  Lee-Chung Lu

IPC分类号： H02H9/04 ,  H03K3/011

CPC分类号： H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H01L27/0285 ,  H03K3/013 ,  H03K5/003 ,  H03K19/003 ,  H03K19/017509

摘要： A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage.

摘要翻译： 公开了电路，多功率域电路和方法。 实施例是包括具有第一输出和第二输出的输入电路的电路，输入电路耦合到第一电源电压，以及电平移动电路，其具有耦合到输入电路的第一输出的第一输入，以及 耦合到所述输入电路的第二输出的第二输入，所述电平移动电路耦合到第二电源电压。 该电路还包括耦合在电平移动电路的第一节点和第二电源电压之间的第一晶体管和具有耦合到第一晶体管的栅极的输出的控制电路，该控制电路耦合到第二电源 电源电压。

公开(公告)号：US08940596B2

公开(公告)日：2015-01-27

申请号：US14058523

申请日：2013-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/02 ,  H01L21/283 ,  H01L21/48 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region.

摘要翻译： 一种方法包括去除结构的栅极层的第一部分。 该结构包括漏极区，源极区和栅极叠层，并且栅极堆叠包括栅极电介质层，直接在栅极介电层上的栅极导电层，以及直接在栅极导电层上的栅极层。 在漏极区域上形成漏极接触区域，在源极区域形成源极接触区域。 导电区域直接形成在栅极导电层上并且邻近栅极层的第二部分。 栅极接触端子形成为与导电区域接触。

公开(公告)号：US08906767B2

公开(公告)日：2014-12-09

申请号：US14106100

申请日：2013-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/36

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20140264616A1

公开(公告)日：2014-09-18

申请号：US13932521

申请日：2013-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/28123 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0266

摘要： An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate devices. The device further includes at least one dummy gate between two epitaxially grown active regions. Each active region is substantially uniform in length.

摘要翻译： 集成电路器件包括生长在衬底上的至少两个外延生长的有源区，该有源区位于两个栅极器件之间。 该器件还包括两个外延生长的有源区之间的至少一个伪栅极。 每个活性区域的长度基本上是均匀的。

公开(公告)号：US20140175551A1

公开(公告)日：2014-06-26

申请号：US13723001

申请日：2012-12-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wun-Jie Lin ,  Bo-Ting Chen ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0255 ,  H01L27/0629 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/861

摘要： A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region.

摘要翻译： 一种结构包括形成在衬底的第一鳍上的N +区，形成在衬底的第二鳍上的P +区，其中P +区和N +区形成二极管，在P +区和 N +区域和形成在浅沟槽隔离区域之间以及N +区域和P +区域之间的第一外延生长块区域，其中二极管的正向偏置电流流过浅沟槽隔离区域下方的路径。

公开(公告)号：US10325906B2

公开(公告)日：2019-06-18

申请号：US15274356

申请日：2016-09-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Heng Chang ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： G01R31/28 ,  H01L27/02 ,  H01L23/62 ,  H01L21/66 ,  G01R31/00

摘要： An electrostatic discharge (ESD) testing structure includes a measurement device in a first die. The ESD testing structure further includes a fuse in a second die. The ESD testing structure further includes a plurality of bonds electrically connecting the first die to the second die, wherein a first bond of the plurality of bonds electrically connects the fuse to the measurement device.

公开(公告)号：US20180040603A1

公开(公告)日：2018-02-08

申请号：US15787992

申请日：2017-10-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ti Su ,  Wun-Jie Lin ,  Han-Jen Yang ,  Shui-Ming Cheng ,  Ming-Hsiang Song

IPC分类号： H01L27/02 ,  H01L27/08 ,  H01L27/06 ,  H01L29/74

CPC分类号： H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/0814 ,  H01L29/7436

摘要： An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

公开(公告)号：US09831235B2

公开(公告)日：2017-11-28

申请号：US14593473

申请日：2015-01-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry-Hak-Lay Chuang ,  Ming-Hsiang Song ,  Kuo-Ji Chen ,  Ming Zhu ,  Po-Nien Chen ,  Bao-Ru Young

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/06

CPC分类号： H01L27/0266 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7835

摘要： A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.