公开(公告)号：US20240332958A1

公开(公告)日：2024-10-03

申请号：US18193684

申请日：2023-03-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tao Yi Hung ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Wun-Jie Lin

IPC分类号： H02H9/04 ,  H02H1/00

CPC分类号： H02H9/046 ,  H02H1/0007

摘要： Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

公开(公告)号：US12046567B2

公开(公告)日：2024-07-23

申请号：US17213630

申请日：2021-03-26

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Tao-Yi Hung ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Wun-Jie Lin

IPC分类号： H01L23/62 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04

CPC分类号： H01L23/60 ,  H01L27/0248 ,  H02H9/046

摘要： A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of second interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.

公开(公告)号：US11862960B2

公开(公告)日：2024-01-02

申请号：US18128693

申请日：2023-03-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hung Yeh ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC分类号： H02H3/08 ,  H02H1/00

CPC分类号： H02H3/08 ,  H02H1/0007

摘要： An electrostatic discharge (ESD) protection circuit includes a first diode, a second diode, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer, and being coupled to the first voltage supply. The first diode is in the semiconductor wafer, and coupled between an IO pad and a first node. The second diode is in the semiconductor wafer, coupled to the first diode and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled between the first node and the second node, and further coupled to the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a first voltage supply. The first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit.

公开(公告)号：US11756953B2

公开(公告)日：2023-09-12

申请号：US17354870

申请日：2021-06-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Hao Chiang ,  Wun-Jie Lin ,  Jam-Wem Lee

IPC分类号： H01L27/02 ,  H01L29/06

CPC分类号： H01L27/0248 ,  H01L29/0649 ,  H01L29/0692

摘要： A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

公开(公告)号：US20200019666A1

公开(公告)日：2020-01-16

申请号：US16263841

申请日：2019-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC分类号： G06F17/50 ,  H01L27/02 ,  G01R31/02

摘要： An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20180040603A1

公开(公告)日：2018-02-08

申请号：US15787992

申请日：2017-10-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ti Su ,  Wun-Jie Lin ,  Han-Jen Yang ,  Shui-Ming Cheng ,  Ming-Hsiang Song

IPC分类号： H01L27/02 ,  H01L27/08 ,  H01L27/06 ,  H01L29/74

CPC分类号： H01L27/0248 ,  H01L27/0262 ,  H01L27/0629 ,  H01L27/0647 ,  H01L27/0814 ,  H01L29/7436

摘要： An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

公开(公告)号：US09876005B2

公开(公告)日：2018-01-23

申请号：US15171812

申请日：2016-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ti Su ,  Han-Jen Yang ,  Wun-Jie Lin ,  Li-Wei Chu

IPC分类号： H01L27/02 ,  H01L21/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861

CPC分类号： H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/861

摘要： An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

公开(公告)号：US20170098645A1

公开(公告)日：2017-04-06

申请号：US15171812

申请日：2016-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ti Su ,  Han-Jen Yang ,  Wun-Jie Lin ,  Li-Wei Chu

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/861

摘要： An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

公开(公告)号：US09312384B2

公开(公告)日：2016-04-12

申请号：US14563720

申请日：2014-12-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Hsiung Lo ,  Jam-Wem Lee ,  Wun-Jie Lin ,  Jen-Chou Tseng

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L29/423

CPC分类号： H01L29/7831 ,  H01L27/0255 ,  H01L29/423 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.

公开(公告)号：US09236733B2

公开(公告)日：2016-01-12

申请号：US13952417

申请日：2013-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Ti Su ,  Wun-Jie Lin ,  Tsung-Che Tsai ,  Jen-Chou Tseng

IPC分类号： H02H9/04 ,  H01L29/74 ,  H01L27/02

CPC分类号： H02H9/046 ,  H01L27/0262 ,  H01L29/7436

摘要： A semiconductor device is disclosed that includes a first well of a first conductivity type, a second well of a second conductivity type, a plurality of first regions, a second region and a plurality of electrodes. The first regions are of the first conductivity type and are formed in the second well. The second region is of the second conductivity type and is formed in the first well. Each of the electrodes is formed upon the second well and between adjacent two first regions of the first regions.

摘要翻译： 公开了一种半导体器件，其包括第一导电类型的第一阱，第二导电类型的第二阱，多个第一区域，第二区域和多个电极。 第一区域是第一导电类型并且形成在第二阱中。 第二区域是第二导电类型并形成在第一阱中。 每个电极形成在第二阱上并且在第一区域的相邻两个第一区域之间。