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公开(公告)号：US11854943B2
公开(公告)日：2023-12-26
申请号：US18153475
申请日：2023-01-12
发明人： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： G11C16/04 , H01L23/48 , H10B10/00 , G11C11/418 , H01L21/768
CPC分类号： H01L23/481 , G11C11/418 , H01L21/76898 , H10B10/18
摘要： An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
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公开(公告)号：US11562946B2
公开(公告)日：2023-01-24
申请号：US17209878
申请日：2021-03-23
发明人： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： G11C11/00 , H01L23/48 , G11C11/418 , H01L21/768 , H01L27/11
摘要： A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.
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公开(公告)号：US20240355384A1
公开(公告)日：2024-10-24
申请号：US18758504
申请日：2024-06-28
IPC分类号： G11C11/419 , G11C11/412 , H10B10/00
CPC分类号： G11C11/419 , G11C11/412 , H10B10/12 , H10B10/18
摘要： A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.
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公开(公告)号：US20230133360A1
公开(公告)日：2023-05-04
申请号：US17825036
申请日：2022-05-26
发明人： Rawan Naous , Kerem Akarvardar , Mahmut Sinangil , Yu-Der Chih , Saman Adham , Nail Etkin Can Akkaya , Hidehiro Fujiwara , Yih Wang , Jonathan Tsung-Yung Chang
摘要： Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.
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公开(公告)号：US20220415373A1
公开(公告)日：2022-12-29
申请号：US17884650
申请日：2022-08-10
摘要： Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.
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公开(公告)号：US11423974B2
公开(公告)日：2022-08-23
申请号：US17241687
申请日：2021-04-27
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096 , G11C5/06 , G11C11/419 , H01L21/48 , H01L27/11
摘要： A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.
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7.发明申请公开(公告)号：US20220236869A1
公开(公告)日：2022-07-28
申请号：US17155362
申请日：2021-01-22
IPC分类号： G06F3/06 , G11C11/419 , G06F7/544
摘要： An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.
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8.发明授权公开(公告)号：US10755768B2
公开(公告)日：2020-08-25
申请号：US16503344
申请日：2019-07-03
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096
摘要： A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.
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公开(公告)号：US10559333B2
公开(公告)日：2020-02-11
申请号：US16404463
申请日：2019-05-06
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
IPC分类号： G11C7/00 , G11C7/12 , G11C7/22 , G11C11/419
摘要： A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.
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公开(公告)号：US10319421B2
公开(公告)日：2019-06-11
申请号：US16005121
申请日：2018-06-11
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
IPC分类号： G11C7/00 , G11C7/12 , G11C7/22 , G11C11/419
摘要： A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.
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