利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.027 秒)

    Duo-level word line driver
    2.
    发明授权
    Duo-level word line driver 有权

    公开(公告)号：US11721393B2

    公开(公告)日：2023-08-08

    申请号：US17592376

    申请日：2022-02-03

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Po-Hao Lee ,  Chia-Fu Lee ,  Yi-Chun Shih

    IPC分类号： G11C7/12 ,  G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/0028

    摘要： A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

    Latch
    4.
    发明授权
    Latch 有权

    公开(公告)号：US11641193B2

    公开(公告)日：2023-05-02

    申请号：US17815322

    申请日：2022-07-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

    IPC分类号： H03K3/356

    摘要： A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.

    Computing-In-Memory Architecture
    6.
    发明申请
    Computing-In-Memory Architecture 有权

    公开(公告)号：US20220415373A1

    公开(公告)日：2022-12-29

    申请号：US17884650

    申请日：2022-08-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

    IPC分类号： G11C7/12 ,  G11C5/06 ,  G11C16/30 ,  G11C7/10 ,  G11C16/04

    摘要： Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

    NEW LOW POWER ADDER TREE STRUCTURE
    7.
    发明申请
    NEW LOW POWER ADDER TREE STRUCTURE 有权

    公开(公告)号：US20220253282A1

    公开(公告)日：2022-08-11

    申请号：US17532632

    申请日：2021-11-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chia-Fu Lee ,  Po-Hao Lee ,  Yi-Chun Shih ,  Yu-Der Chih

    IPC分类号： G06F7/501 ,  G06F7/506 ,  H03K19/0185 ,  H03K19/21

    摘要： In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

    MEMORY SENSE AMPLIFIER TRIMMING
    8.
    发明申请
    MEMORY SENSE AMPLIFIER TRIMMING 有权

    公开(公告)号：US20220093142A1

    公开(公告)日：2022-03-24

    申请号：US17543046

    申请日：2021-12-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C29/42 ,  G11C11/16

    摘要： A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

    Memory sense amplifier trimming
    9.
    发明授权
    Memory sense amplifier trimming 有权

    公开(公告)号：US11227640B2

    公开(公告)日：2022-01-18

    申请号：US16870220

    申请日：2020-05-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC分类号： G11C7/08 ,  G11C7/06 ,  G11C11/16 ,  G11C29/42 ,  G11C7/10

    摘要： A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.