公开(公告)号：US11916151B2

公开(公告)日：2024-02-27

申请号：US17357997

申请日：2021-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chia-Ming Hsu ,  Yi-Jing Li ,  Chih-Hsin Ko ,  Kuang-Hsin Chen ,  Da-Wen Lin ,  Clement Hsingjen Wann

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742

摘要： Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

公开(公告)号：US11861282B2

公开(公告)日：2024-01-02

申请号：US18065275

申请日：2022-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Hsiang Huang ,  Fong-Yuan Chang ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Sheng-Hsiung Chen ,  Li-Chun Tien ,  Chia-Ming Hsu

IPC分类号： G06F30/3312 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  G06F111/20

CPC分类号： G06F30/392 ,  G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785 ,  G06F2111/20

摘要： A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.

公开(公告)号：US11942467B2

公开(公告)日：2024-03-26

申请号：US17351240

申请日：2021-06-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： I-Sheng Chen ,  Yi-Jing Li ,  Chia-Ming Hsu ,  Wan-Lin Tsai ,  Clement Hsingjen Wann

IPC分类号： H01L23/64 ,  H01L21/70 ,  H01L27/01 ,  H01L49/02

CPC分类号： H01L27/016 ,  H01L21/707 ,  H01L28/60

摘要： A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

公开(公告)号：US11508627B2

公开(公告)日：2022-11-22

申请号：US17067193

申请日：2020-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yi-Jing Lee ,  Ya-Yun Cheng ,  Hau-Yu Lin ,  I-Sheng Chen ,  Chia-Ming Hsu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

摘要： A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

公开(公告)号：US11080453B2

公开(公告)日：2021-08-03

申请号：US16599552

申请日：2019-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Po-Hsiang Huang ,  Sheng-Hsiung Chen ,  Chih-Hsin Ko ,  Fong-Yuan Chang ,  Clement Hsingjen Wann ,  Li-Chun Tien ,  Chia-Ming Hsu

IPC分类号： G11C11/4076 ,  G11C11/4094 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G06F30/392 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3312 ,  G06F111/20

摘要： A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

公开(公告)号：US11908749B2

公开(公告)日：2024-02-20

申请号：US18057741

申请日：2022-11-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yi-Jing Lee ,  Ya-Yun Cheng ,  Hau-Yu Lin ,  I-Sheng Chen ,  Chia-Ming Hsu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L23/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/823842 ,  H01L21/02068 ,  H01L21/28088 ,  H01L21/321 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/66545

摘要： A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

公开(公告)号：US11568122B2

公开(公告)日：2023-01-31

申请号：US17376413

申请日：2021-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Hsiang Huang ,  Fong-Yuan Chang ,  Clement Hsingjen Wann ,  Chih-Hsin Ko ,  Sheng-Hsiung Chen ,  Li-Chun Tien ,  Chia-Ming Hsu

IPC分类号： G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  G06F30/392 ,  G06F111/20

摘要： A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

公开(公告)号：US10804163B2

公开(公告)日：2020-10-13

申请号：US16372178

申请日：2019-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yi-Jing Lee ,  Ya-Yun Cheng ,  Hau-Yu Lin ,  I-Sheng Chen ,  Chia-Ming Hsu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/321 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

摘要： A method of forming a semiconductor structure includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; removing the barrier layer from the first trench to expose the dielectric layer; depositing a work function layer over the dielectric layer in the first trench; and depositing a conductive layer over the work function layer in the first trench.