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公开(公告)号：US20230060423A1
公开(公告)日：2023-03-02
申请号：US17986119
申请日：2022-11-14
IPC分类号： H01L29/66 , H01L29/04 , H01L29/78 , H01L21/02 , H01L21/306 , H01L29/16 , H01L29/161 , H01L29/165 , H01L21/762 , H01L29/06 , H01L29/08
摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
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公开(公告)号：US11508627B2
公开(公告)日：2022-11-22
申请号：US17067193
申请日：2020-10-09
发明人： Yi-Jing Lee , Ya-Yun Cheng , Hau-Yu Lin , I-Sheng Chen , Chia-Ming Hsu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/49 , H01L21/321 , H01L21/02 , H01L21/28 , H01L29/66
摘要： A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
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公开(公告)号：US11362000B2
公开(公告)日：2022-06-14
申请号：US16865049
申请日：2020-05-01
发明人： Sung-Li Wang , Neng-Kuo Chen , Ding-Kang Shih , Meng-Chun Chang , Yi-An Lin , Gin-Chen Huang , Chen-Feng Hsu , Hau-Yu Lin , Chih-Hsin Ko , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/00 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/06 , H01L29/417 , H01L27/088 , H01L29/423 , H01L29/51
摘要： A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
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公开(公告)号：US20220173245A1
公开(公告)日：2022-06-02
申请号：US17671042
申请日：2022-02-14
发明人： Tsung-Lin Lee , Chih-Hao Chang , Chih-Hsin Ko , Feng Yuan , Jeff J. Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165 , H01L21/76 , H01L21/02 , H01L21/306 , H01L21/31 , H01L21/311 , H01L29/06 , H01L29/08
摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
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公开(公告)号：US20210036131A1
公开(公告)日：2021-02-04
申请号：US17063459
申请日：2020-10-05
IPC分类号： H01L29/66 , H01L29/04 , H01L29/78 , H01L21/02 , H01L21/306 , H01L29/16 , H01L29/161 , H01L29/165 , H01L21/762 , H01L29/06 , H01L29/08
摘要： The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
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公开(公告)号：US20200258784A1
公开(公告)日：2020-08-13
申请号：US16865049
申请日：2020-05-01
发明人： Sung-Li Wang , Neng-Kuo Chen , Ding-Kang Shih , Meng-Chun Chang , Yi-An Lin , Gin-Chen Huang , Chen-Feng Hsu , Hau-Yu Lin , Chih-Hsin Ko , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/66 , H01L29/51 , H01L29/423 , H01L29/417 , H01L29/06 , H01L27/088 , H01L29/16 , H01L29/161 , H01L29/165 , H01L21/8238
摘要： A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
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7.发明授权公开(公告)号：US10727351B2
公开(公告)日：2020-07-28
申请号：US16390866
申请日：2019-04-22
IPC分类号： H01L29/78 , H01L29/267 , H01L29/10 , H01L29/66 , H01L21/02 , H01L29/778 , H01L21/762 , H01L21/8252 , H01L29/06 , H01L29/205
摘要： An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
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8.发明申请公开(公告)号：US20190252546A1
公开(公告)日：2019-08-15
申请号：US16390866
申请日：2019-04-22
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/205 , H01L21/02 , H01L21/762 , H01L21/8252 , H01L29/778 , H01L29/267 , H01L29/06
CPC分类号： H01L29/7851 , H01L21/0259 , H01L21/02636 , H01L21/02639 , H01L21/02658 , H01L21/76224 , H01L21/8252 , H01L29/0649 , H01L29/1037 , H01L29/1054 , H01L29/205 , H01L29/267 , H01L29/66462 , H01L29/66522 , H01L29/66795 , H01L29/7786 , H01L29/7842 , H01L29/7848 , H01L29/785
摘要： An embodiment is a structure comprising a substrate, a high energy bandgap material, and a high carrier mobility material. The substrate comprises a first isolation region and a second isolation region. Each of first and second isolation regions extends below a first surface of the substrate between the first and second isolation regions. The high energy bandgap material is over the first surface of the substrate and is disposed between the first and second isolation regions. The high carrier mobility material is over the high energy bandgap material. The high carrier mobility material extends higher than respective top surfaces of the first and second isolation regions to form a fin.
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公开(公告)号：US10263091B2
公开(公告)日：2019-04-16
申请号：US15379067
申请日：2016-12-14
发明人： Yee-Chia Yeo , Chih Chieh Yeh , Chih-Hsin Ko , Cheng-Hsien Wu , Liang-Yin Chen , Xiong-Fei Yu , Yen-Ming Chen , Chan-Lon Yang
IPC分类号： H01L29/76 , H01L29/49 , H01L29/10 , H01L29/66 , H01L29/165 , H01L21/28 , H01L29/51 , H01L29/78 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/423 , H01L29/786
摘要： A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.
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公开(公告)号：US09899521B2
公开(公告)日：2018-02-20
申请号：US15058344
申请日：2016-03-02
发明人： Sung-Li Wang , Ding-Kang Shih , Chih-Hsin Ko
IPC分类号： H01L31/072 , H01L31/109 , H01L29/78 , H01L29/66 , H01L21/3205 , H01L23/485 , H01L29/417 , H01L21/768 , H01L21/28 , H01L21/285 , H01L29/06 , H01L21/02
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28247 , H01L21/285 , H01L21/28512 , H01L21/32051 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L21/76843 , H01L21/76856 , H01L23/485 , H01L29/0653 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
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