公开(公告)号：US20240274687A1

公开(公告)日：2024-08-15

申请号：US18647521

申请日：2024-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hung CHU ,  Kan-Ju Lin ,  Hsu-Kai Chang ,  Chien Chang ,  Tzu-Pei Chen ,  Hung-Yi Huang ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC分类号： H01L29/45 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/45 ,  H01L21/31116 ,  H01L21/823475 ,  H01L23/53242 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791

摘要： The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US20240055491A1

公开(公告)日：2024-02-15

申请号：US17885577

申请日：2022-08-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hung Chu ,  Shuen-Shin Liang ,  Chung-Liang Cheng ,  Sung-Li Wang ,  Chien Chang ,  Harry CHIEN ,  Lin-Yu Huang ,  Min-Hsuan Lu

IPC分类号： H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/41733 ,  H01L29/458 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775

摘要： A semiconductor device includes parallel channel members, a gate structure, source/drain features, a silicide layer, and a source/drain contact. The parallel channel members are spaced apart from one another. The gate structure is wrapping around the channel members. The source/drain features are disposed besides the channel members and at opposite sides of the gate structure. The silicide layer is disposed on and in direct contact with the source/drain features. The source/drain contact is disposed on the silicide layer, wherein the source/drain contact includes a first source/drain contact and a second source/drain contact stacked on the first source/drain contact, and the second source/drain contact is separate from the silicide layer by the first source/drain contact.

公开(公告)号：US20240021687A1

公开(公告)日：2024-01-18

申请号：US18191750

申请日：2023-03-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Wei Chang ,  Chien Chang ,  Kan-Ju Lin ,  Harry Chien ,  Shuen-Shin Liang ,  Chia-Hung Chu ,  Sung-Li Wang ,  Shahaji B. More ,  Yueh-Ching Pai

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/41791 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823418

摘要： A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.

公开(公告)号：US20200176260A1

公开(公告)日：2020-06-04

申请号：US16265747

申请日：2019-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

摘要： A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

公开(公告)号：US11817384B2

公开(公告)日：2023-11-14

申请号：US17567525

申请日：2022-01-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5228

摘要： The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

公开(公告)号：US11217524B1

公开(公告)日：2022-01-04

申请号：US16900622

申请日：2020-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shuen-Shin Liang ,  Ken-Yu Chang ,  Hung-Yi Huang ,  Chien Chang ,  Chi-Hung Chuang ,  Kai-Yi Chu ,  Chun-I Tsai ,  Chun-Hsien Huang ,  Chih-Wei Chang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Keng-Chu Lin ,  Sung-Li Wang

IPC分类号： H01L23/522 ,  H01L21/768

摘要： The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

公开(公告)号：US11107690B2

公开(公告)日：2021-08-31

申请号：US16265747

申请日：2019-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

摘要： A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.