公开(公告)号：US09716090B2

公开(公告)日：2017-07-25

申请号：US15193628

申请日：2016-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Hong-Yi Wu ,  Shiu-Ko Jangjian ,  Wei-Ming You ,  Ting-Chun Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/788 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.

公开(公告)号：US09406675B1

公开(公告)日：2016-08-02

申请号：US14658511

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Hong-Yi Wu ,  Shiu-Ko Jangjian ,  Wei-Ming You ,  Ting-Chun Wang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/788 ,  H01L27/088 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the substrate, forming shallow trench isolations over the substrate, and forming an oxide material over the fin structure. The method further includes forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer over the oxide material, wherein the forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer includes doping carbon in a range of from about 5E19/cm3 to about 1E22/cm3.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括提供基板，形成从基板挤出的翅片结构，在基底上形成浅沟槽隔离，以及在翅片结构上形成氧化物材料。 所述方法还包括在所述氧化物材料上形成碳掺杂非晶硅层或碳掺杂多晶硅层，其中形成碳掺杂非晶硅层或碳掺杂多晶硅层包括在一定范围内掺杂碳 约5E19 / cm3至约1E22 / cm3。