公开(公告)号：US20240355784A1

公开(公告)日：2024-10-24

申请号：US18758167

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

公开(公告)号：US11664411B2

公开(公告)日：2023-05-30

申请号：US17238041

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Che Lee ,  Sheng-Chau Chen ,  I-Nan Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L49/02 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/3171 ,  H01L23/5227 ,  H01L24/05 ,  H01L27/01 ,  H01L2224/11

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

公开(公告)号：US10541297B2

公开(公告)日：2020-01-21

申请号：US16205065

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Che Lee ,  I-Nan Chen ,  Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L27/14 ,  H01L49/02 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

公开(公告)号：US20220262770A1

公开(公告)日：2022-08-18

申请号：US17729286

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/532

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via(TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

公开(公告)号：US11011600B2

公开(公告)日：2021-05-18

申请号：US16744793

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Che Lee ,  I-Nan Chen ,  Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L49/02 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.

公开(公告)号：US10658409B2

公开(公告)日：2020-05-19

申请号：US15903560

申请日：2018-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Sheng-Chan Li ,  I-Nan Chen ,  Tzu-Hsiang Chen ,  Yu-Jen Wang ,  Yen-Ting Chiang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L27/146 ,  H01L21/763 ,  H01L21/762

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

公开(公告)号：US11374046B2

公开(公告)日：2022-06-28

申请号：US16849975

申请日：2020-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Sheng-Chan Li ,  I-Nan Chen ,  Tzu-Hsiang Chen ,  Yu-Jen Wang ,  Yen-Ting Chiang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L27/146 ,  H01L21/763 ,  H01L21/762

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

公开(公告)号：US10164001B1

公开(公告)日：2018-12-25

申请号：US15707240

申请日：2017-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Che Lee ,  I-Nan Chen ,  Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L27/14 ,  H01L29/82 ,  H01L49/02 ,  H01L23/31 ,  H01L27/01 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.