公开(公告)号：US12022743B2

公开(公告)日：2024-06-25

申请号：US17395962

申请日：2021-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tsann Lin ,  Ya-Ling Lee

IPC: H10N50/80 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85 ,  H01F10/3286

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a buffer layer, a seed layer disposed over the buffer layer, a reference layer disposed over the seed layer, a tunnel barrier layer disposed over the reference layer and a free layer disposed over the tunnel barrier layer. The seed layer includes a Cobalt (Co)-based film. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US20230261063A1

公开(公告)日：2023-08-17

申请号：US17674811

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Ling Lee ,  Wei-Gang Chiu ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L21/443 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/45 ,  H01L29/401 ,  H01L21/443 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.

公开(公告)号：US12069961B2

公开(公告)日：2024-08-20

申请号：US18331154

申请日：2023-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ya-Ling Lee ,  Tsann Lin ,  Han-Jong Chia

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G01R33/093 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US20240006538A1

公开(公告)日：2024-01-04

申请号：US17857021

申请日：2022-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Po-Ting Lin ,  Kai-Wen Cheng ,  Sai-Hooi Yeong ,  Han-Ting Tsai ,  Ya-Ling Lee ,  Hai-Ching Chen ,  Chung-Te Lin ,  Yu-Ming Lin

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/1159

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L27/1159

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

公开(公告)号：US11716909B2

公开(公告)日：2023-08-01

申请号：US17070426

申请日：2020-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ya-Ling Lee ,  Tsann Lin ,  Han-Jong Chia

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G01R33/093 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MU element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TIM coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US12075709B2

公开(公告)日：2024-08-27

申请号：US17377753

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Ling Lee ,  Wei-Gang Chiu ,  Ming-Hsing Tsai

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: One or more semiconductor processing tools may deposit one or more tantalum nitride layers on an upper surface of a copper interconnect and within a via. The one or more semiconductor processing tools may deposit an adhesion layer on an upper surface of the one or more tantalum nitride layers and within the via. The one or more semiconductor processing tools may deposit tungsten on an upper surface of the adhesion layer and within the via for via interconnection of the magnetic tunnel junction to the copper interconnect.

公开(公告)号：US20240081081A1

公开(公告)日：2024-03-07

申请号：US18152151

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Ling Lee ,  Chung-Te Lin ,  Han-Ting Tsai ,  Wei-Gang Chiu ,  Yen-Chieh Huang ,  Ming-Yi Yang

IPC: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.

公开(公告)号：US20220231036A1

公开(公告)日：2022-07-21

申请号：US17716330

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Ling Lee ,  Wei-Gang Chiu ,  Yen-Chieh Huang ,  Han-Ting Tsai ,  Tsann Lin ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11507 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).