公开(公告)号：US08975961B2

公开(公告)日：2015-03-10

申请号：US13902389

申请日：2013-05-24

Applicant: Texas Instruments Incorporated

Inventor： Alok Prakash Joshi ,  Gireesh Rajendran

IPC: H03F3/45

CPC classification number: H03G1/00 ,  H03F3/211 ,  H03F3/24

Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.

Abstract translation: 公开了用于降低功率放大器电路中功耗的电路。 在某些实施例中，用于发射机中功率控制的电路包括耦合电路，第一功率放大器电路和第二功率放大器电路。 耦合电路包括与第一次级绕组和第二次级绕组感应地相关联的初级绕组。 耦合电路响应于初级绕组处的信号在第一次级绕组和第二次级绕组的输出端提供信号。 第一功率放大器电路与第一次级绕组的输出端耦合，第二功率放大器与第二次级绕组的输出端耦合。 第一功率放大器电路和第二功率放大器电路被配置为基于偏置电压被使能或禁用。

公开(公告)号：US20140347124A1

公开(公告)日：2014-11-27

申请号：US13902389

申请日：2013-05-24

Applicant: Texas Instruments Incorporated

Inventor： Alok Prakash Joshi ,  Gireesh Rajendran

IPC: H03G1/00

CPC classification number: H03G1/00 ,  H03F3/211 ,  H03F3/24

Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.

Abstract translation: 公开了用于降低功率放大器电路中功耗的电路。 在某些实施例中，用于发射机中功率控制的电路包括耦合电路，第一功率放大器电路和第二功率放大器电路。 耦合电路包括与第一次级绕组和第二次级绕组感应地相关联的初级绕组。 耦合电路响应于初级绕组处的信号在第一次级绕组和第二次级绕组的输出端提供信号。 第一功率放大器电路与第一次级绕组的输出端耦合，第二功率放大器与第二次级绕组的输出端耦合。 第一功率放大器电路和第二功率放大器电路被配置为基于偏置电压被使能或禁用。

公开(公告)号：US20140312474A1

公开(公告)日：2014-10-23

申请号：US13866200

申请日：2013-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alok Prakash Joshi ,  Gireesh Rajendran ,  Brian Parks

IPC: H01L23/00

CPC classification number: H01L24/49 ,  H01L23/3107 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/00

Abstract: A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire.

Abstract translation: 具有具有多个电连续芯线接合位置的管芯的半导体封装包括第一管芯接合位置和第二管芯接合部位。 该封装包括具有包括第一衬底引线接合位置和第二衬底引线接合部位的多个电连续衬底引线接合位置的衬底。 第一接合线连接在第一芯线接合部位和第一基板引线接合位置之间，第二接合线连接在第二芯线接合部位和第二基板引线接合部位之间。 第一和第二焊丝线位于相邻的基本上平行的接合线平面中。 第二接合线相对于所述第一接合线基本上是倾斜的。