公开(公告)号：US20190206828A1

公开(公告)日：2019-07-04

申请号：US16025603

申请日：2018-07-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin GUO ,  Jason CHIEN ,  Byron Lovell WILLIAMS ,  Jeffrey Alan WEST ,  Anderson LI ,  Arvin Nono VERDEFLOR

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/49 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49505 ,  H01L2224/85013 ,  H01L2224/85913 ,  H01L2924/1205

Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

公开(公告)号：US20150061081A1

公开(公告)日：2015-03-05

申请号：US14536897

申请日：2014-11-10

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan WEST ,  Thomas D. BONIFIELD ,  Basab CHATTERJEE

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract translation: 一种集成电路，其包含将集成电路的内部区域与紧邻集成电路外部的划片线分隔开的裂纹偏转划线密封件及其形成方法。 裂纹偏转划线密封件包括连续金属层和连续金属层之间的连续接触和连续通孔。 连续金属层不延伸经过连续接触和连续通孔。 连续接触和连续的通孔从划线密封的划线侧的下面的连续金属层的边缘凹陷，在划线密封件上提供成角度的外表面，其可以期望地终止裂纹扩展或将裂纹传播向上偏转到顶部表面 划线或裂纹偏转划痕。

公开(公告)号：US20200251440A1

公开(公告)日：2020-08-06

申请号：US16854823

申请日：2020-04-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Honglin GUO ,  Jason CHIEN ,  Byron Lovell WILLIAMS ,  Jeffrey Alan WEST ,  Anderson LI ,  Arvin Nono VERDEFLOR

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56

Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

公开(公告)号：US20200168534A1

公开(公告)日：2020-05-28

申请号：US16202663

申请日：2018-11-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer BONIFIELD ,  Sreeram Subramanyam NASUM ,  Robert H. EKLUND ,  Jeffrey Alan WEST ,  Byron Lovell WILLIAMS ,  Elizabeth Costner STEWART

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: In some examples, a multi-chip module (MCM), comprises a first and a second die-attach pad (DAP); a first die comprising a first set of microelectronic devices; a second die comprising a first capacitor and a second capacitor; and a third die comprising a second set of microelectronic devices, where the first and second dies are positioned on the first DAP, and the third die is positioned on the second DAP. The first set of microelectronic devices couples to the first capacitor via a first inter-die connection and the second set of microelectronic devices couples to the second capacitor via a second inter-die connection.