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公开(公告)号：US20250080120A1
公开(公告)日：2025-03-06
申请号：US18952296
申请日：2024-11-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
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公开(公告)号：US10962632B2
公开(公告)日：2021-03-30
申请号：US15845290
申请日：2017-12-18
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Espen Wium , Tomas Motos , Hagen Clemens Graf
Abstract: Electronic devices and methods to provide wireless ranging are shown. A first electronic device includes a memory containing stored instructions that can perform a method for determining a distance between the first electronic device and a second electronic device. For each frequency in a selected set of frequencies, the method sets the transceiver to the respective frequency, sends a first tone having the frequency and a first phase to the second electronic device and receives a second tone having the first frequency and a second phase. For each selected frequency, the first electronic device determines the phase difference between the second tone and the controllable oscillator, receives a phase difference from the second electronic device, and calculates a phase delay for the frequency. The first electronic device calculates a phase delay difference for pairs of the frequencies; and determines the distance using these phase delay differences.
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公开(公告)号：US12170522B2
公开(公告)日：2024-12-17
申请号：US18175683
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
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公开(公告)号：US09628262B1
公开(公告)日：2017-04-18
申请号：US15213574
申请日：2016-07-19
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe
CPC classification number: H04L7/0331 , H03L7/183 , H03L7/197 , H04B15/02 , H04L7/06
Abstract: An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.
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公开(公告)号：US11736269B2
公开(公告)日：2023-08-22
申请号：US17488364
申请日：2021-09-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Wenxun Qiu , Tomas Motos , Marius Moe
IPC: H04L7/04 , H04L27/34 , H04L27/38 , H04B1/7073
CPC classification number: H04L7/042 , H04B1/70735 , H04L27/3405 , H04L27/3455 , H04L27/3836 , H04B2201/7073 , H04L2212/00
Abstract: A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.
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Patent Agency Ranking
公开(公告)号：US11595046B2
公开(公告)日：2023-02-28
申请号：US17515598
申请日：2021-11-01
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
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公开(公告)号：US20200212916A1
公开(公告)日：2020-07-02
申请号：US16232911
申请日：2018-12-26
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
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公开(公告)号：US12273852B2
公开(公告)日：2025-04-08
申请号：US17537882
申请日：2021-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Anand Dabak , Marius Moe , Charles Sestok
Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.
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公开(公告)号：US20250030427A1
公开(公告)日：2025-01-23
申请号：US18524711
申请日：2023-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Hagen Graf , Tarjei Aaberge
Abstract: A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.
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公开(公告)号：US20230208425A1
公开(公告)日：2023-06-29
申请号：US18175683
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
CPC classification number: H03L7/085 , H03L7/0812 , H03K5/14 , H03K3/0315 , H03K2005/00019
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
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