-
公开(公告)号：US20250080120A1
公开(公告)日：2025-03-06
申请号：US18952296
申请日：2024-11-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
公开(公告)号：US11595046B2
公开(公告)日：2023-02-28
申请号：US17515598
申请日：2021-11-01
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
公开(公告)号：US20200212916A1
公开(公告)日：2020-07-02
申请号：US16232911
申请日：2018-12-26
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
公开(公告)号：US12174659B2
公开(公告)日：2024-12-24
申请号：US17824695
申请日：2022-05-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Atul Ramakant Lele , Dirk Preikszat , Gregory North , Robin Osa Hoel , Tarjei Aaberge
Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.
-
公开(公告)号：US12170522B2
公开(公告)日：2024-12-17
申请号：US18175683
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
Patent Agency Ranking
公开(公告)号：US20250030427A1
公开(公告)日：2025-01-23
申请号：US18524711
申请日：2023-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Hagen Graf , Tarjei Aaberge
Abstract: A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.
-
公开(公告)号：US20230208425A1
公开(公告)日：2023-06-29
申请号：US18175683
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge
CPC classification number: H03L7/085 , H03L7/0812 , H03K5/14 , H03K3/0315 , H03K2005/00019
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
公开(公告)号：US11196426B2
公开(公告)日：2021-12-07
申请号：US17087978
申请日：2020-11-03
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
公开(公告)号：US11762340B2
公开(公告)日：2023-09-19
申请号：US17390291
申请日：2021-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Marius Moe , Tarjei Aaberge , Bijit Patel
CPC classification number: G04F10/005 , H03K3/0315
Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.
-
公开(公告)号：US20210075427A1
公开(公告)日：2021-03-11
申请号：US17087978
申请日：2020-11-03
Applicant: Texas Instruments Incorporated
Inventor： Marius Moe , Tarjei Aaberge
Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.013 seconds)
