公开(公告)号：US20180261531A1

公开(公告)日：2018-09-13

申请号：US15978497

申请日：2018-05-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Allen Gerber

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

公开(公告)号：US20150041994A1

公开(公告)日：2015-02-12

申请号：US14453650

申请日：2014-08-07

Applicant: Texas Instruments Incorporated

Inventor： Mark Allen Gerber

IPC: H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract translation: 一种半导体器件（100），包括在第一水平平面（180）中具有组装焊盘（121）的引线框（120），所述焊盘的第一表面（121a）具有附接的半导体芯片（110） 另外在与附接芯片的方向上偏离第一平面的平行的第二水平面（190）中的多个引线（122），引线具有带有接合线的第三表面（122a）和相对的第四表面（122b） ）; 封装引线框，芯片和电线的封装（140），所述封装具有平行于所述第一和第二平面的第五表面（140a）; 在所述封装体中的多个凹部孔（150），每个孔从各个引线的第五面到第四面延伸; 和焊料（160）填充凹槽，焊料附着到第四引线表面并延伸到第五封装表面。

公开(公告)号：US20160240392A1

公开(公告)日：2016-08-18

申请号：US15137114

申请日：2016-04-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

公开(公告)号：US09253910B2

公开(公告)日：2016-02-02

申请号：US13900758

申请日：2013-05-23

Applicant: Texas Instruments Incorporated

Inventor： Mark Allen Gerber

IPC: H05K7/00 ,  H05K7/02 ,  H05K1/18

CPC classification number: H05K7/02 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/19103 ,  H01L2924/19105 ,  H05K1/182 ,  H05K2201/09072 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49117 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract translation: 电路组件包括具有衬底电路，相对的顶部和底部衬底表面以及延伸穿过衬底的衬底孔的衬底。 电路组件还包括电连接到基板电路的分立组件组件和附接到分立组件的支撑构件。 离散部件的至少一部分物理地安装在基板孔中。

公开(公告)号：US09978667B2

公开(公告)日：2018-05-22

申请号：US14453650

申请日：2014-08-07

Applicant: Texas Instruments Incorporated

Inventor： Mark Allen Gerber

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48639 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

公开(公告)号：US20150147845A1

公开(公告)日：2015-05-28

申请号：US14552548

申请日：2014-11-25

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Mark Allen Gerber ,  Mutsumi Masumoto ,  Masamitsu Matsuura ,  Kengo Aoya ,  Takeshi Onogami

IPC: H01L25/00 ,  H01L21/304 ,  H01L21/683 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract translation: 本发明的实施例提供了一种用于形成双面嵌入式模具系统的方法。 该方法从起始材料开始，包括顶表面和底表面，多个通孔，多个电镀金属柱，冲压垫和加强件。 将表面平坦化以暴露所包含的金属，其不是从管芯附着垫DAP区域选择性地蚀刻以形成空腔。 通过使用光刻胶图案和电镀创建一个加强筋。 涂抹胶带。 附上一个模具 层压和研磨。 去除胶带。 形式重新分配层RDL和焊接掩模。 安装表面贴装器件。

公开(公告)号：US20140211444A1

公开(公告)日：2014-07-31

申请号：US13900749

申请日：2013-05-23

Applicant: Texas Instruments Incorporated

Inventor： Mark Allen Gerber

IPC: H05K7/02 ,  H05K3/32

CPC classification number: H05K7/02 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/19103 ,  H01L2924/19105 ,  H05K1/182 ,  H05K2201/09072 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49117 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A discrete component assembly includes a discrete component having a central longitudinal axis and having an outer surface with a laterally outermost point positioned at a first radial distance from the central longitudinal axis. The assembly includes a support structure mounted on the discrete component. The assembly also includes a plurality of contact pads electrically connected to the discrete component and mounted on the support structure at radial distances from the central longitudinal axis greater than the first radial distance.

Abstract translation: 分立部件组件包括具有中心纵向轴线并具有外表面的分立部件，外表面具有定位在离中心纵向轴线的第一径向距离处的横向最外侧点。 组件包括安装在分立部件上的支撑结构。 该组件还包括多个电连接到分立元件的接触垫，并且以大于第一径向距离的中心纵向轴线的径向距离安装在支撑结构上。

公开(公告)号：US10510643B2

公开(公告)日：2019-12-17

申请号：US15978497

申请日：2018-05-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Allen Gerber

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

公开(公告)号：US20140211439A1

公开(公告)日：2014-07-31

申请号：US13900758

申请日：2013-05-23

Applicant: Texas Instruments Incorporated

Inventor： Mark Allen Gerber

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K7/02 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/19103 ,  H01L2924/19105 ,  H05K1/182 ,  H05K2201/09072 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49117 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract translation: 电路组件包括具有衬底电路，相对的顶部和底部衬底表面以及延伸穿过衬底的衬底孔的衬底。 电路组件还包括电连接到基板电路的分立组件组件和附接到分立组件的支撑构件。 离散部件的至少一部分物理地安装在基板孔中。