公开(公告)号：US20240405024A1

公开(公告)日：2024-12-05

申请号：US18534056

申请日：2023-12-08

Applicant: Texas Instruments Incorporated

Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Zhikai Tang ,  Timothy Merkin ,  Jungwoo Joh

IPC: H01L27/095 ,  H01L27/02 ,  H01L29/20 ,  H01L29/778

Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

公开(公告)号：US20240405078A1

公开(公告)日：2024-12-05

申请号：US18326698

申请日：2023-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Johan Strydom ,  Zhikai Tang ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

公开(公告)号：US20240105450A1

公开(公告)日：2024-03-28

申请号：US18090766

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yoganand Saripalli ,  Russell Fields ,  Brian Goodlin ,  Qhalid Fareed

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/44 ,  C30B25/08 ,  C30B29/40 ,  H01J37/32

CPC classification number: H01L21/02661 ,  C23C16/301 ,  C23C16/4405 ,  C30B25/08 ,  C30B29/40 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01J37/32816 ,  H01J2237/332

Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.