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公开(公告)号：US20250138633A1
公开(公告)日：2025-05-01
申请号：US18694280
申请日：2022-09-23
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor： Nader Fathy , Patrick Mercier
Abstract: A method for obtaining neural signals from a neural signal sensor includes extracting sensor offset from a neural input signal. Sensor offset is removed from N-channels that share a single amplifier. The neural input signal is acquired from the analog domain by neural electrodes with varying DC-offset and the method includes multiplexing the N-channels via a time divisional multiple access procedure into a single neural amplifier An integrated digitally assisted neural recording system includes an analog multiplexer structured to receive N-channels and to multiplex the N-Channels into a single neural amplifier. A feedback loop is configured to cancel electrode offset voltage in the digital domain by generating electrode offset voltage samples and adding delay to align each electrode offset voltage sample to be subtracted at the neural amplifier in the analog domain.
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公开(公告)号：US20210242877A1
公开(公告)日：2021-08-05
申请号：US17285289
申请日：2019-10-14
Applicant: The Regents of the University of California
Inventor： Hui Wang , Patrick Mercier
Abstract: A charging to digital converter sensor in a CMOS integrated circuit digitizes a sensed property by comparing charging time between two paths and adjusting the charging rate of one of the two paths by increasing or decreasing the amount of capacitance in that path, until both of the two paths have the same charging time to reach respective constant with sensed property and proportional with sensed property reference voltages or currents. Sub nanowatt operation is achieved with preferred circuits. A method directly digitizes, on-chip, a charging time comparison of two ramp voltages that are compared to respective constant with sensed property and proportional with sensed property reference voltages or currents.
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3.发明授权公开(公告)号：US10701495B2
公开(公告)日：2020-06-30
申请号：US15502130
申请日：2015-08-07
Applicant: The Regents of the University of California , San Diego State University Research Foundation
Inventor： Truong Nguyen , Harinath Garudadri , Patrick Mercier , Arthur Boothroyd , Carol Mackersie
Abstract: A hearing assistance and/or noise suppression device leverages computing power of an external device with a digital signal processor, such as a special unit that is configured to communicate with a smart device (e.g., a smart phone, smart watch or smart pendant) or a smart phone with a digital signal processor. Methods include having a hearing transducer communicate with and offload computing tasks to an external device with a digital signal processor. Systems include a hearing transducer with transducer circuitry that receives, amplifies and outputs digital signal processed audio from another device. Methods provide self-adjustment and fitting through a touch screen interface, which can be conducted outside of a clinical setting in a real world environment, and method can include remote data collection and communications with clinicians.
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公开(公告)号：US10348300B2
公开(公告)日：2019-07-09
申请号：US15887178
申请日：2018-02-02
Applicant: The Regents of the University of California
Inventor： Loai Galal Bahgat Salem , Patrick Mercier
IPC: H03K19/00 , H03K3/012 , H03K19/017 , G11C11/4074 , H03K19/096 , G11C5/14
Abstract: A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage VDD and ground and inner switches to at least one capacitance that self-balances between VDD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage VDD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between VDD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.
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公开(公告)号：US20180226969A1
公开(公告)日：2018-08-09
申请号：US15887178
申请日：2018-02-02
Applicant: The Regents of the University of California
Inventor： Loai Galal Bahgat Salem , Patrick Mercier
IPC: H03K19/00 , H03K3/012 , G11C5/14 , G11C11/4074 , H03K19/096 , H03K19/017
CPC classification number: H03K19/0019 , G11C5/147 , G11C11/4074 , H03K3/012 , H03K19/017 , H03K19/0963
Abstract: A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage VDD and ground and inner switches to at least one capacitance that self-balances between VDD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage VDD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between VDD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.
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Patent Agency Ranking
公开(公告)号：US20180019667A1
公开(公告)日：2018-01-18
申请号：US15545614
申请日：2016-01-29
Applicant: The Regents of the University of California
Inventor： Loai Galal Bahgat Salem , Patrick Mercier
IPC: H02M3/07
CPC classification number: H02M3/07
Abstract: A scalable controller circuit that provides faster and simpler regulation of a DC-to-DC converter is provided. Unlike such prior techniques, preferred embodiments do not require any threshold-level generation circuitry or analog compensation circuitry. Preferred embodiments implement a simple control law that requires only a few digital gates. Preferred embodiments can therefore significantly reduce the overhead power consumption and area of the controller in DC-to-DC converters to new levels.
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公开(公告)号：US20240187986A1
公开(公告)日：2024-06-06
申请号：US18553617
申请日：2022-03-31
Applicant: The Regents of the University of California
Inventor： Manideep Dunna , Miao Meng , Po-Han Peter Wang , Chi Zhang , Patrick Mercier , Dinesh Bharadia
IPC: H04W52/02
CPC classification number: H04W52/0216 , H04W52/0235
Abstract: A method for waking a transceiver for communicating directly with commodity Wi-Fi transceivers (TRXs) via backscatter modulation in an integrated tag device includes sensing an incident Wi-Fi-compliant wake-up signal with a wake-up stage. Upon wake-up, a payload packet is sensed with a sync stage, the sync stage having higher bandwidth and power than the wake-up stage, the sync stage enabling a backscatter transmission circuit in sync with the payload. A backscatter transceiver includes a wake-up receiver having an energy-detection based architecture and having circuitry to conduct a counter-based wake up responsive to two pre-specified WiFi compatible packets. A sync receiver is enabled by the wake-up receiver upon reception of the two pre-specified WiFi compatible packets, the sync receiver including circuitry to detect a payload packet and create a backscatter enable signal synced with a payload of the payload packet. A backscatter transmitter is enabled by the backscatter enable signal.
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公开(公告)号：US20230046820A1
公开(公告)日：2023-02-16
申请号：US17798554
申请日：2021-02-10
Inventor： Abraham Akinin , Gert Cauwenberghs , Chul Kim , Patrick Mercier , Hiren Thacker
Abstract: Apparatuses and methods are disclosed for efficient wireless powering of an electrical load with precise external control over pulsed voltage waveform and metering of charge delivered. The system interfaces to an inductive coil for RF power delivery from an external duty-cycled RF power transmitter, and the electrical load. The electrical load may be a photosensitive array of electrodes for an optically addressed, electrically activated retinal prosthesis. The voltage waveform to activate the load is controlled by the transmitted RF amplitude, including switching between cathodic and anodic phases of electrical stimulation. Charge delivered to the load is quantified as discharge events through a series capacitor, transmitted by backtelemetry to the receiver for continuous monitoring throughout the stimulation phases. The subject disclosure further provides for calibration of voltage amplitude and charge metering, to compensate for variable wireless link and load conditions, through additional stimulation phases with a supplementary load with known and stable characteristics.
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公开(公告)号：US11570709B2
公开(公告)日：2023-01-31
申请号：US16742476
申请日：2020-01-14
Applicant: The Regents of the University of California
Inventor： Po-Han Wang , Patrick Mercier
Abstract: A low-power wake-up receiver includes a mixer-based two-stage heterodyne architecture that provides multi-stage channel filtering, including a combination of circuits and a digital signal processor that process energy in a plurality of advertising channels to detect a four-dimensional wake-up signature via frequency-hopping among the plurality of advertising channels. One receiver is a BLE/Wi-Fi dual-mode wake-up receiver.
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公开(公告)号：US11356017B2
公开(公告)日：2022-06-07
申请号：US16843175
申请日：2020-04-08
Applicant: The Regents of the University of California
Inventor： Sally Amin , Patrick Mercier
IPC: H02M3/07 , H03K3/356 , H02J7/00 , H01M10/0525
Abstract: A DC-DC converter converts voltage from a battery source providing a voltage Vin to a lower level. A four-level transistor stack selectively connects an input voltage and flying capacitor voltages to an output inductor. Stress reduction transistors limit the charging of the flying capacitors to Vin/3. The stress reduction transistors can also limit switching transistor voltages to Vin/3. Freewheel switches can be used to limit ringing in the output inductor.
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