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公开(公告)号：US10574228B2
公开(公告)日：2020-02-25
申请号：US15103387
申请日：2014-11-14
发明人： Yusuke Fujita , Satoshi Miura , Shunichi Kubo
IPC分类号： H03K17/16 , H03K17/693 , H03K19/00 , H03K19/173 , H04J3/04
摘要： The signal multiplexer 1 inputs two selection signals CLK , CLK that sequentially reach significant levels, inputs two input signals IN , IN , and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN of the two input signals when an m-th selection signal CLK of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.
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公开(公告)号：US20190123700A1
公开(公告)日：2019-04-25
申请号：US16164151
申请日：2018-10-18
发明人： Yusuke Fujita
IPC分类号： H03F3/45
摘要： A transmission/reception system includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.
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公开(公告)号：US10148418B2
公开(公告)日：2018-12-04
申请号：US15302068
申请日：2015-03-11
发明人： Yusuke Fujita , Satoshi Miura , Shunichi Kubo
摘要： A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.
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公开(公告)号：US11329669B2
公开(公告)日：2022-05-10
申请号：US16972349
申请日：2019-06-19
发明人： Satoshi Miura , Yusuke Fujita
摘要： A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.
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公开(公告)号：US10333507B2
公开(公告)日：2019-06-25
申请号：US15546509
申请日：2017-01-06
发明人： Yusuke Fujita , Shunichi Kubo , Yoshinobu Oshima
摘要： A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.
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6.发明授权公开(公告)号：US11323182B2
公开(公告)日：2022-05-03
申请号：US17359955
申请日：2021-06-28
发明人： Yusuke Fujita
摘要： A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.
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公开(公告)号：US10924073B2
公开(公告)日：2021-02-16
申请号：US16164151
申请日：2018-10-18
发明人： Yusuke Fujita
摘要： A transmission/reception system 1 includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112 that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.
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公开(公告)号：US10715152B2
公开(公告)日：2020-07-14
申请号：US16419222
申请日：2019-05-22
发明人： Shunichi Kubo , Yusuke Fujita
摘要： A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.
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公开(公告)号：US12066972B2
公开(公告)日：2024-08-20
申请号：US18017263
申请日：2021-08-11
发明人： Yusuke Fujita
CPC分类号： G06F13/4282 , G06F13/382 , G06F2213/0042
摘要： The communication device 111 included in the active cable comprises a controller 11, a comparator 12, a resistor 13, a voltage source 14, and a redriver 16. The comparator 12 receives the voltage value of the SBU signal line and the reference voltage value output from the voltage source 14, and compares the voltage value of the SBU signal line with the reference voltage value to detect the level of the sideband signal. The controller 11 receives the detection result of the sideband signal level from the comparator 12, and sets the redriver 16, which is an active device, to the low-power-consumption state when the sideband signal level stays at L level for a predetermined period of time or longer.
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公开(公告)号：US11206029B2
公开(公告)日：2021-12-21
申请号：US16591679
申请日：2019-10-03
发明人： Yusuke Fujita , Yuji Gendai
摘要： A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.
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