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公开(公告)号：US20070002618A1
公开(公告)日：2007-01-04
申请号：US11427337
申请日：2006-06-28
IPC分类号： G11C11/34
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译： 存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换为第一状态 状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时， 电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流 电阻元件的第二端子，以便将电阻元件转换成第二端子 状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。
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公开(公告)号：US07400526B2
公开(公告)日：2008-07-15
申请号：US11427337
申请日：2006-06-28
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译： 存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换成第一状态 状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时， 电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流 电阻元件的第二端子，以便将电阻元件转换成第二端子 状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。
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公开(公告)号：US20070002619A1
公开(公告)日：2007-01-04
申请号：US11427339
申请日：2006-06-28
IPC分类号： G11C11/34
CPC分类号： G11C14/009 , G11C13/0004
摘要： The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for non-volatile saving of the stored information and a means for saving the information in the resistance element. A means for retrieving the saved information is additionally present.
摘要翻译： 非易失性存储单元具有用于存储二进制信息项的易失性存储装置。 此外，存储单元仅包括用于非易失性地存储信息的单个可编程电阻元件和用于将信息保存在电阻元件中的装置。 另外存在用于检索保存的信息的装置。
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公开(公告)号：US07359232B2
公开(公告)日：2008-04-15
申请号：US11427336
申请日：2006-06-28
申请人： Thomas Niedermeier , Tim Schoenauer
发明人： Thomas Niedermeier , Tim Schoenauer
IPC分类号： G11C7/00
CPC分类号： G11C7/24 , G11C7/1006 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C14/009 , G11C2213/74
摘要： The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.
摘要翻译： 多上下文存储单元包括用于存储数据信息项的第一存储器装置和多个第二存储器装置，存储在第一存储器装置中的数据信息可以被保存在每个第二存储器装置中。 此外，存储单元包括用于将存储在第一存储器装置中的数据信息保存到第二存储装置之一的装置，以及用于将存储在所选择的第二存储装置中的数字数据信息存储到第一存储装置中的装置。
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公开(公告)号：US20070002606A1
公开(公告)日：2007-01-04
申请号：US11427336
申请日：2006-06-28
申请人： Thomas Niedermeier , Tim Schoenauer
发明人： Thomas Niedermeier , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C7/24 , G11C7/1006 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C14/009 , G11C2213/74
摘要： The multi-context memory cell comprises a first memory means for storing an item of data information and also a plurality of second memory means, it being possible for the data information stored in the first memory means to be saved in each second memory means. Moreover, the memory cell comprises a means for saving the data information stored in the first memory means into one of the second memory means, and also a means for storing the digital data information stored in a selected second memory means into the first memory means.
摘要翻译： 多上下文存储单元包括用于存储数据信息项的第一存储器装置和多个第二存储器装置，存储在第一存储器装置中的数据信息可以被保存在每个第二存储器装置中。 此外，存储单元包括用于将存储在第一存储器装置中的数据信息保存到第二存储装置之一的装置，以及用于将存储在所选择的第二存储装置中的数字数据信息存储到第一存储装置中的装置。
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公开(公告)号：US07177385B2
公开(公告)日：2007-02-13
申请号：US11004047
申请日：2004-12-03
IPC分类号： G11C19/00
CPC分类号： H03K19/17748 , G11C8/04 , G11C19/00 , G11C19/28 , H03K19/177
摘要： The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be connected to the master latch for the purpose of buffer storing the data bit; at least one second slave latch which can be connected to the master latch for the purpose of buffer storing the data bit, and having an evaluation logic unit which outputs the configuration bit on the basis of the data bits which are buffer stored in the master latch and in the slave latches. In addition, the invention provides a shift register for safely providing configuration bits which has a plurality of inventive shift register cells which are connected in series to form a shift register chain.
摘要翻译： 本发明涉及一种用于安全地提供具有主锁存器的配置位的移位寄存器单元，其可以连接到移位寄存器单元上输入的串行数据，以便缓冲存储数据位; 第一从锁存器，其可以连接到主锁存器，用于缓冲器存储数据位; 至少一个第二从锁存器，其可以连接到主锁存器，用于存储数据位的缓冲器，并且具有评估逻辑单元，其基于存储在主锁存器中的缓冲器的数据位输出配置位 和从机锁存器。 此外，本发明提供了一种用于安全地提供配置位的移位寄存器，其具有串联连接以形成移位寄存器链的多个本发明的移位寄存器单元。
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7.发明授权Method for operation of a bus system for highly flexible and quick data transmission between units connected to the bus system and configuration for carrying out the method 失效用于总线系统的操作方法，用于在连接到总线系统的单元之间进行高度灵活和快速的数据传输以及用于执行该方法的配置
公开(公告)号：US5828852A
公开(公告)日：1998-10-27
申请号：US562802
申请日：1995-11-27
申请人： Thomas Niedermeier , Peter Rohm , Richard Schmid , David Flynn , Peter Klapproth , Frederik Zandveld , Jacobus Christophorus Koot , Andrew Michael Jones , James Graham Matthew , Bruno Douady
发明人： Thomas Niedermeier , Peter Rohm , Richard Schmid , David Flynn , Peter Klapproth , Frederik Zandveld , Jacobus Christophorus Koot , Andrew Michael Jones , James Graham Matthew , Bruno Douady
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.
摘要翻译： 一种用于总线系统操作的方法和电路配置。 总线包括总线控制单元，其仅控制仲裁，并且在数据传输期间超过时间。 在相应的主动主单元和寻址的从单元中确定实际的数据传输。 诸如数据长度，对数据区域或控制区域的访问和等待周期的总线周期的特性通过多个控制线以编码形式被传送。
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公开(公告)号：US20070247196A1
公开(公告)日：2007-10-25
申请号：US11400349
申请日：2006-04-07
申请人： Thomas Niedermeier , Tim Schonauer
发明人： Thomas Niedermeier , Tim Schonauer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/0013 , H03K19/1733
摘要： A circuit and method for configuring a circuit is disclosed. In one embodiment, the circuit includes at least one pull-down path, wherein an amount of a current flowing through the pull-down path is determined by a switchable resistivity value of a switchable resistor that is included by the circuit. The invention further provides method for configuring a circuit and to a logic circuit.
摘要翻译： 公开了一种用于配置电路的电路和方法。 在一个实施例中，电路包括至少一个下拉路径，其中流过下拉路径的电流量由电路所包含的可切换电阻器的可切换电阻率值确定。 本发明还提供了一种用于配置电路和逻辑电路的方法。
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公开(公告)号：US20050163277A1
公开(公告)日：2005-07-28
申请号：US11004047
申请日：2004-12-03
IPC分类号： G11C8/04 , G11C19/00 , G11C19/28 , H03K19/177
CPC分类号： H03K19/17748 , G11C8/04 , G11C19/00 , G11C19/28 , H03K19/177
摘要： Shift register for safely providing a configuration bit The invention relates to a shift register cell (1-i, 100-i) for safely providing a configuration bit (6-i) having a master latch (8-i) which can be connected to a serial data input (2-i) on the shift register cell (1-i, 100-i) for the purpose of buffer-storing a data bit (3-i); a first slave latch (10-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit; at least one second slave latch (12-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit, and having an evaluation logic unit (13-i) which outputs the configuration bit (6-i) on the basis of the data bits which are buffer-stored in the master latch (8-i) and in the slave latches (10-i, 12-i). In addition, the invention provides a shift register (17) for safely providing configuration bits (6-1, . . . 6-N) which has a plurality of inventive shift register cells (1-1, . . . 1-N, 100-1, . . . 100-N) which are connected in series to form a shift register chain (1, 100).
摘要翻译： 用于安全地提供配置位的移位寄存器技术领域本发明涉及一种用于安全地提供具有主锁存器（8-i）的配置位（6-i）的移位寄存器单元（1-i，100i），其可以连接到 用于缓冲存储数据位（3-i）的移位寄存器单元（1 -i，100-i）上的串行数据输入（2-i）; 第一从锁存器（10-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位; 至少一个第二从锁存器（12-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位，并具有输出配置的评估逻辑单元（13-i） 基于缓冲存储在主锁存器（8-i）和从锁存器（10 -i-12-i）中的数据位来执行位（6-i）。 另外，本发明提供了一种用于安全地提供配置位（6-1，...，6-N）的移位寄存器（17），其具有多个本发明的移位寄存器单元（1至1，...， 100 -1，...，100 -N），其串联连接以形成移位寄存器链（1,100）。
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