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公开(公告)号：US07400526B2
公开(公告)日：2008-07-15
申请号：US11427337
申请日：2006-06-28
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译： 存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换成第一状态 状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时， 电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流 电阻元件的第二端子，以便将电阻元件转换成第二端子 状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。
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公开(公告)号：US20070002619A1
公开(公告)日：2007-01-04
申请号：US11427339
申请日：2006-06-28
IPC分类号： G11C11/34
CPC分类号： G11C14/009 , G11C13/0004
摘要： The non-volatile memory cell has a volatile memory means for storing an item of binary information. Furthermore, the memory cell comprises only a single programmable resistance element for non-volatile saving of the stored information and a means for saving the information in the resistance element. A means for retrieving the saved information is additionally present.
摘要翻译： 非易失性存储单元具有用于存储二进制信息项的易失性存储装置。 此外，存储单元仅包括用于非易失性地存储信息的单个可编程电阻元件和用于将信息保存在电阻元件中的装置。 另外存在用于检索保存的信息的装置。
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公开(公告)号：US20070002618A1
公开(公告)日：2007-01-04
申请号：US11427337
申请日：2006-06-28
IPC分类号： G11C11/34
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译： 存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换为第一状态 状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时， 电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流 电阻元件的第二端子，以便将电阻元件转换成第二端子 状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。
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公开(公告)号：US07436694B2
公开(公告)日：2008-10-14
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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公开(公告)号：US20070047292A1
公开(公告)日：2007-03-01
申请号：US11444295
申请日：2006-05-31
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。
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公开(公告)号：US09443583B2
公开(公告)日：2016-09-13
申请号：US13270592
申请日：2011-10-11
申请人： Christian Pacha , Tim Schönauer , Michael Kund
发明人： Christian Pacha , Tim Schönauer , Michael Kund
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L27/2436 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/145
摘要： A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
摘要翻译： 存储器件包括具有接触区域的翅片的多栅极场效应晶体管（MuGFET）。 可编程存储元件邻接鳍片接触区域。
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公开(公告)号：US07561460B2
公开(公告)日：2009-07-14
申请号：US11688556
申请日：2007-03-20
申请人： Corvin Liaw , Thomas Roehr , Michael Kund
发明人： Corvin Liaw , Thomas Roehr , Michael Kund
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C2213/78 , G11C2213/79
摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
摘要翻译： 提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的驱动元件的电阻性存储单元的电阻式存储器装置。 每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。
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公开(公告)号：US07457145B2
公开(公告)日：2008-11-25
申请号：US11092969
申请日：2005-03-30
申请人： Michael Kund , Thomas Happ
发明人： Michael Kund , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0064 , G11C13/0069
摘要： The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.
摘要翻译： 本发明涉及一种用于操作存储器单元的系统，存储器组件和用于操作存储单元的过程，其包括活性材料，其可以通过适当的切换过程改变为或多或少的导电状态，由此该过程包括（a）带来 存储器单元进入或多或少的导电状态，并且在将存储单元改变为或多或少的导电状态之后评估存储单元的状态。
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9.发明申请Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product 审中-公开集成电路，存储器模块，集成电路的操作方法，制造集成电路的方法和计算机程序产品公开(公告)号：US20080259676A1
公开(公告)日：2008-10-23
申请号：US11736439
申请日：2007-04-17
申请人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
发明人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
CPC分类号： G11C13/0011 , B82Y10/00 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C29/50 , G11C2013/0083 , G11C2213/32 , G11C2213/71 , G11C2213/79
摘要： According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell.
摘要翻译： 根据本发明的一个实施例，提供一种集成电路，其包括多个电阻率变化单元。 至少两个电阻范围被分配给每个电阻率变化单元，每个电阻范围限定电阻率变化单元的可能状态。 集成电路可以在将初始化信号施加到电阻率变化单元的单元初始化模式中操作。 选择初始化信号的强度和持续时间，使得每个电阻率变化单元的电阻被转移到分配给电阻率变化单元的电阻范围之一。
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公开(公告)号：US20070053224A1
公开(公告)日：2007-03-08
申请号：US11515421
申请日：2006-09-05
申请人： Thomas Happ , Michael Kund
发明人： Thomas Happ , Michael Kund
IPC分类号： G11C16/04
CPC分类号： G11C13/0011 , G11C13/0069 , G11C16/3495
摘要： Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).
摘要翻译： 用于编程导电桥接RAM（CBRAM）存储单元的方法和设备通过确保在重新写入之前擦除存储单元来提高周期稳定性。 可选地，在重写存储器单元的情况下，仅当写入操作将改变单元内容时（即，存储在存储单元中的位的状态正在从逻辑0改变为逻辑1 或相反亦然）。
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