公开(公告)号：US20250079184A1

公开(公告)日：2025-03-06

申请号：US18241773

申请日：2023-09-01

Applicant: Tokyo Electron Limited

Inventor： Jason MARION ,  Alexander KAISER ,  Yusuke YOSHIDA ,  Yun HAN

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/40 ,  H01L29/66

Abstract: A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

公开(公告)号：US20160027620A1

公开(公告)日：2016-01-28

申请号：US14807319

申请日：2015-07-23

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jason MARION ,  Sonam SHERPA ,  Sergey A. VORONIN ,  Alok RANJAN ,  Yoshio ISHIKAWA ,  Takashi ENOMOTO

IPC: H01J37/32

CPC classification number: H01J37/32697 ,  H01J37/32422 ,  H01J37/32706 ,  H01J37/32715 ,  H01L21/6833

Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.

Abstract translation: 提供了一种等离子体处理方法和装置，其中当存在处理等离子体时，使与静电卡盘（ESC）的电压施加相关联的电流尖峰被最小化或减小。 根据一个例子，在处理等离子体被击打之后，电压被施加到ESC，然而电压以逐步方式倾斜或增加以达到期望的最终ESC电压。 在替代实施例中，ESC电压至少部分地施加在等离子体撞击之前用于处理晶片。 通过在处理等离子体的存在期间减少与电压施加相关联的电流尖峰，可以减少颗粒在晶片上的转移或沉积。

公开(公告)号：US20250006504A1

公开(公告)日：2025-01-02

申请号：US18343124

申请日：2023-06-28

Applicant: Tokyo Electron Limited

Inventor： Jason MARION ,  Indroneil ROY ,  Yusuke YOSHIDA ,  Yun HAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/762

Abstract: A method includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. The method includes forming a metal layer over the dielectric layer. The method includes forming a patterned mask over the metal layer. The method includes performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer. The method further includes performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns.