公开(公告)号：US20250079184A1

公开(公告)日：2025-03-06

申请号：US18241773

申请日：2023-09-01

Applicant: Tokyo Electron Limited

Inventor： Jason MARION ,  Alexander KAISER ,  Yusuke YOSHIDA ,  Yun HAN

IPC: H01L21/3213 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/40 ,  H01L29/66

Abstract: A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.

公开(公告)号：US20220359718A1

公开(公告)日：2022-11-10

申请号：US17721551

申请日：2022-04-15

Applicant: Tokyo Electron Limited

Inventor： Yun HAN ,  Eric Chih-Fang LIU ,  Kai-Hung YU ,  Shihsheng CHANG ,  Alok RANJAN

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311

Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

公开(公告)号：US20220344162A1

公开(公告)日：2022-10-27

申请号：US17721014

申请日：2022-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yun HAN ,  Alok RANJAN ,  Peter VENTZEK ,  Andrew METZ ,  Hiroaki NIIMI

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

公开(公告)号：US20250006504A1

公开(公告)日：2025-01-02

申请号：US18343124

申请日：2023-06-28

Applicant: Tokyo Electron Limited

Inventor： Jason MARION ,  Indroneil ROY ,  Yusuke YOSHIDA ,  Yun HAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/762

Abstract: A method includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. The method includes forming a metal layer over the dielectric layer. The method includes forming a patterned mask over the metal layer. The method includes performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer. The method further includes performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns.

公开(公告)号：US20220344169A1

公开(公告)日：2022-10-27

申请号：US17724088

申请日：2022-04-19

Applicant: Tokyo Electron Limited

Inventor： Yun HAN ,  David L. O'MEARA ,  Cheryl ALIX ,  Andrew METZ ,  Shan HU ,  Henan ZHANG

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: A method includes providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate with a dielectric spacer separating each source/drain contact region from adjacent metal gate stacks. Each source/drain region is recessed within an opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the recess and dielectric spacers provide sidewalls. The etch stop layer is formed on the substrate such that it conformally covers the metal gate stacks, the sidewalls and the bottom of each recess, and a sacrificial layer is formed over each of the metal gate stacks and on at least a portion of each sidewall. The etch stop layer is removed from the bottom of each recess to expose the source/drain contact, and the sacrificial layer is then removed from the metal gate stacks and the sidewalls of each recess.

公开(公告)号：US20220384199A1

公开(公告)日：2022-12-01

申请号：US17721620

申请日：2022-04-15

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yun HAN ,  Andrew METZ ,  Peter BIOLSI

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.