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1.
公开(公告)号:US20180026141A1
公开(公告)日:2018-01-25
申请号:US15714393
申请日:2017-09-25
Applicant: TOPPAN PRINTING CO., LTD.
Inventor: Noriaki IKEDA , Makoto NISHIZAWA
IPC: H01L29/786 , H01L21/283 , H01L27/12 , G02F1/136 , H01L29/66 , H01L29/417 , H01L21/768
CPC classification number: H01L29/7869 , G02F1/136 , H01L21/28 , H01L21/283 , H01L21/768 , H01L23/532 , H01L27/1259 , H01L27/3258 , H01L27/3274 , H01L29/41733 , H01L29/6675 , H01L29/786 , H01L51/0545
Abstract: A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.
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公开(公告)号:US20170222168A1
公开(公告)日:2017-08-03
申请号:US15492333
申请日:2017-04-20
Applicant: TOPPAN PRINTING CO., LTD.
Inventor: Noriaki IKEDA
IPC: H01L51/05 , H01L51/00 , H01L29/417 , H01L29/66 , H01L29/786 , H01L29/423
CPC classification number: H01L51/0545 , H01L29/41733 , H01L29/42384 , H01L29/66757 , H01L29/66765 , H01L29/78696 , H01L51/0003 , H01L51/105 , H01L51/107
Abstract: A thin-film transistor including a substrate, a gate electrode positioned on the substrate, a gate insulating layer positioned on the substrate and the gate electrode, a source electrode positioned on the gate insulating layer, a drain electrode positioned on the gate insulating layer, a semiconductor layer connected to the source electrode and the drain electrode, and a protective layer positioned on the semiconductor layer. The source electrode and the drain electrode each have a surface including asperities.
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3.
公开(公告)号:US20190189942A1
公开(公告)日:2019-06-20
申请号:US16283666
申请日:2019-02-22
Applicant: TOPPAN PRINTING CO., LTD.
Inventor: Noriaki IKEDA , Makoto NISHIZAWA
CPC classification number: H01L51/105 , G09F9/30 , H01L21/28 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786 , H01L51/05 , H01L51/0541 , H01L51/0545
Abstract: An organic thin-film transistor includes an insulating substrate, a capacitor electrode formed on the insulating substrate, a first insulating layer covering the capacitor electrode, a gate electrode formed on the first insulating layer, a second insulating layer covering the gate electrode and the capacitor electrode, a source electrode formed on the second insulating layer, a drain electrode formed on the second insulating layer, and a semiconductor layer formed on the second insulating layer in a portion between the source electrode and the drain electrode and including an organic semiconductor material.
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公开(公告)号:US20160285019A1
公开(公告)日:2016-09-29
申请号:US15080924
申请日:2016-03-25
Applicant: TOPPAN PRINTING CO., LTD.
Inventor: Minoru KUMAGAI , Noriaki IKEDA
CPC classification number: H01L51/107 , G02F1/1368 , G02F1/167 , H01L27/1248 , H01L27/1292 , H01L27/283 , H01L27/3248 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/005 , H01L51/0055 , H01L51/0094 , H01L51/0096 , H01L51/0545
Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
Abstract translation: 薄膜晶体管阵列包括基板,形成在基板上的栅极电极,覆盖栅电极的栅极绝缘膜,形成在栅极绝缘膜上的源电极,形成在栅极绝缘膜上的漏电极,连接到半导体层 形成在漏电极和半导体层上的层间绝缘膜和形成在层间绝缘膜上的像素电极。 层间绝缘膜具有到达漏电极的一部分的通孔,漏电极在位于通孔中的部分上具有防液涂层。
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